73 lines
1.7 KiB
ArmAsm
73 lines
1.7 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl1.h>
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#include <bl_common.h>
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.globl bl1_aarch32_smc_handler
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func bl1_aarch32_smc_handler
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/* ------------------------------------------------
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* SMC in BL1 is handled assuming that the MMU is
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* turned off by BL2.
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* ------------------------------------------------
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*/
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/* ----------------------------------------------
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* Only RUN_IMAGE SMC is supported.
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* ----------------------------------------------
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*/
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mov r8, #BL1_SMC_RUN_IMAGE
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cmp r8, r0
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blne report_exception
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/* ------------------------------------------------
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* Make sure only Secure world reaches here.
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* ------------------------------------------------
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*/
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ldcopr r8, SCR
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tst r8, #SCR_NS_BIT
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blne report_exception
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/* ---------------------------------------------------------------------
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* Pass control to next secure image.
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* Here it expects r1 to contain the address of a entry_point_info_t
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* structure describing the BL entrypoint.
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* ---------------------------------------------------------------------
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*/
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mov r8, r1
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mov r0, r1
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bl bl1_print_next_bl_ep_info
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#if SPIN_ON_BL1_EXIT
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bl print_debug_loop_message
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debug_loop:
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b debug_loop
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#endif
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mov r0, r8
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bl bl1_plat_prepare_exit
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stcopr r0, TLBIALL
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dsb sy
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isb
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/*
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* Extract PC and SPSR based on struct `entry_point_info_t`
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* and load it in LR and SPSR registers respectively.
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*/
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ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
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ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
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msr spsr, r1
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add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
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ldm r8, {r0, r1, r2, r3}
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eret
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endfunc bl1_aarch32_smc_handler
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