436 lines
14 KiB
C
436 lines
14 KiB
C
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <gic_v2.h>
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#include <gic_v3.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <stdint.h>
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/* Value used to initialize Non-Secure IRQ priorities four at a time */
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#define GICD_IPRIORITYR_DEF_VAL \
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(GIC_HIGHEST_NS_PRIORITY | \
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(GIC_HIGHEST_NS_PRIORITY << 8) | \
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(GIC_HIGHEST_NS_PRIORITY << 16) | \
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(GIC_HIGHEST_NS_PRIORITY << 24))
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static uintptr_t g_gicc_base;
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static uintptr_t g_gicd_base;
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static uintptr_t g_gicr_base;
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static const unsigned int *g_irq_sec_ptr;
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static unsigned int g_num_irqs;
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/*******************************************************************************
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* This function does some minimal GICv3 configuration. The Firmware itself does
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* not fully support GICv3 at this time and relies on GICv2 emulation as
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* provided by GICv3. This function allows software (like Linux) in later stages
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* to use full GICv3 features.
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******************************************************************************/
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static void gicv3_cpuif_setup(void)
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{
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unsigned int val;
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uintptr_t base;
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/*
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* When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
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* bit set. In order to allow interrupts to get routed to the CPU we
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* need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
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* to clear (GICv3 Architecture specification 5.4.23).
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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*/
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assert(g_gicr_base);
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base = gicv3_get_rdist(g_gicr_base, read_mpidr());
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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* configured.
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*/
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panic();
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}
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val = gicr_read_waker(base);
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val &= ~WAKER_PS;
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gicr_write_waker(base, val);
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dsb();
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/* We need to wait for ChildrenAsleep to clear. */
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val = gicr_read_waker(base);
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while (val & WAKER_CA)
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val = gicr_read_waker(base);
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val = read_icc_sre_el3();
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write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
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isb();
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}
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/*******************************************************************************
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* This function does some minimal GICv3 configuration when cores go
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* down.
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******************************************************************************/
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static void gicv3_cpuif_deactivate(void)
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{
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unsigned int val;
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uintptr_t base;
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/*
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* When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
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* wait for GICR_WAKER.ChildrenAsleep to get set.
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* (GICv3 Architecture specification 5.4.23).
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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*/
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assert(g_gicr_base);
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base = gicv3_get_rdist(g_gicr_base, read_mpidr());
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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* configured.
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*/
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panic();
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}
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val = gicr_read_waker(base);
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val |= WAKER_PS;
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gicr_write_waker(base, val);
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dsb();
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/* We need to wait for ChildrenAsleep to set. */
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val = gicr_read_waker(base);
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while ((val & WAKER_CA) == 0)
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val = gicr_read_waker(base);
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}
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/*******************************************************************************
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* Enable secure interrupts and use FIQs to route them. Disable legacy bypass
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* and set the priority mask register to allow all interrupts to trickle in.
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******************************************************************************/
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void arm_gic_cpuif_setup(void)
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{
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unsigned int val;
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assert(g_gicc_base);
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val = gicc_read_iidr(g_gicc_base);
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/*
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* If GICv3 we need to do a bit of additional setup. We want to
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* allow default GICv2 behaviour but allow the next stage to
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* enable full gicv3 features.
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
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gicv3_cpuif_setup();
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val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
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gicc_write_ctlr(g_gicc_base, val);
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}
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* as result of an asserted interrupt. This is critical for powering down a cpu
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******************************************************************************/
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void arm_gic_cpuif_deactivate(void)
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{
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unsigned int val;
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/* Disable secure, non-secure interrupts and disable their bypass */
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assert(g_gicc_base);
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val = gicc_read_ctlr(g_gicc_base);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(g_gicc_base, val);
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val = gicc_read_iidr(g_gicc_base);
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/*
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* If GICv3 we need to do a bit of additional setup. Make sure the
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* RDIST is put to sleep.
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
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gicv3_cpuif_deactivate();
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}
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/*******************************************************************************
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* boot/hotplug. This marks out the secure interrupts & enables them.
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******************************************************************************/
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void arm_gic_pcpu_distif_setup(void)
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{
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unsigned int index, irq_num, sec_ppi_sgi_mask;
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assert(g_gicd_base);
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/* Setup PPI priorities doing four at a time */
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for (index = 0; index < 32; index += 4) {
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gicd_write_ipriorityr(g_gicd_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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assert(g_irq_sec_ptr);
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sec_ppi_sgi_mask = 0;
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/* Ensure all SGIs and PPIs are Group0 to begin with */
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gicd_write_igroupr(g_gicd_base, 0, 0);
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for (index = 0; index < g_num_irqs; index++) {
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irq_num = g_irq_sec_ptr[index];
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if (irq_num < MIN_SPI_ID) {
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/* We have an SGI or a PPI */
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sec_ppi_sgi_mask |= 1U << irq_num;
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gicd_set_ipriorityr(g_gicd_base, irq_num,
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GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_isenabler(g_gicd_base, irq_num);
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}
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}
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/*
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* Invert the bitmask to create a mask for non-secure PPIs and
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* SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
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* update the GICR_IGROUPR0 as well in case we are running on a GICv3
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* system. This is critical if GICD_CTLR.ARE_NS=1.
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*/
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gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask);
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}
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/*******************************************************************************
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* Get the current CPU bit mask from GICD_ITARGETSR0
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******************************************************************************/
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static unsigned int arm_gic_get_cpuif_id(void)
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{
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unsigned int val;
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val = gicd_read_itargetsr(g_gicd_base, 0);
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return val & GIC_TARGET_CPU_MASK;
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}
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/*******************************************************************************
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* Global gic distributor setup which will be done by the primary cpu after a
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* cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
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* then enables the secure GIC distributor interface.
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******************************************************************************/
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static void arm_gic_distif_setup(void)
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{
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unsigned int num_ints, ctlr, index, irq_num;
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uint8_t target_cpu;
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/* Disable the distributor before going further */
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assert(g_gicd_base);
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ctlr = gicd_read_ctlr(g_gicd_base);
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ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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gicd_write_ctlr(g_gicd_base, ctlr);
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/*
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* Mark out non-secure SPI interrupts. The number of interrupts is
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* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
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*/
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num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
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num_ints = (num_ints + 1) << 5;
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for (index = MIN_SPI_ID; index < num_ints; index += 32)
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gicd_write_igroupr(g_gicd_base, index, ~0);
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/* Setup SPI priorities doing four at a time */
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for (index = MIN_SPI_ID; index < num_ints; index += 4) {
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gicd_write_ipriorityr(g_gicd_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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/* Read the target CPU mask */
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target_cpu = arm_gic_get_cpuif_id();
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/* Configure SPI secure interrupts now */
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assert(g_irq_sec_ptr);
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for (index = 0; index < g_num_irqs; index++) {
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irq_num = g_irq_sec_ptr[index];
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if (irq_num >= MIN_SPI_ID) {
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/* We have an SPI */
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gicd_clr_igroupr(g_gicd_base, irq_num);
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gicd_set_ipriorityr(g_gicd_base, irq_num,
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GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu);
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gicd_set_isenabler(g_gicd_base, irq_num);
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}
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}
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/*
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* Configure the SGI and PPI. This is done in a separated function
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* because each CPU is responsible for initializing its own private
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* interrupts.
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*/
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arm_gic_pcpu_distif_setup();
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gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
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}
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/*******************************************************************************
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* Initialize the ARM GIC driver with the provided platform inputs
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******************************************************************************/
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void arm_gic_init(uintptr_t gicc_base,
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uintptr_t gicd_base,
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uintptr_t gicr_base,
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const unsigned int *irq_sec_ptr,
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unsigned int num_irqs)
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{
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unsigned int val;
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assert(gicc_base);
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assert(gicd_base);
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assert(irq_sec_ptr);
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g_gicc_base = gicc_base;
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g_gicd_base = gicd_base;
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val = gicc_read_iidr(g_gicc_base);
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
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assert(gicr_base);
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g_gicr_base = gicr_base;
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}
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g_irq_sec_ptr = irq_sec_ptr;
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g_num_irqs = num_irqs;
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}
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/*******************************************************************************
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* Setup the ARM GIC CPU and distributor interfaces.
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******************************************************************************/
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void arm_gic_setup(void)
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{
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arm_gic_cpuif_setup();
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arm_gic_distif_setup();
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}
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/*******************************************************************************
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* An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
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* The interrupt controller knows which pin/line it uses to signal a type of
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* interrupt. This function provides a common implementation of
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* plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
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* across platforms. It lets the interrupt management framework determine
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* for a type of interrupt and security state, which line should be used in the
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* SCR_EL3 to control its routing to EL3. The interrupt line is represented as
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* the bit position of the IRQ or FIQ bit in the SCR_EL3.
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******************************************************************************/
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uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
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uint32_t security_state)
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{
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assert(type == INTR_TYPE_S_EL1 ||
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type == INTR_TYPE_EL3 ||
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type == INTR_TYPE_NS);
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assert(sec_state_is_valid(security_state));
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/*
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* We ignore the security state parameter under the assumption that
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* both normal and secure worlds are using ARM GICv2. This parameter
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* will be used when the secure world starts using GICv3.
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*/
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#if ARM_GIC_ARCH == 2
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return gicv2_interrupt_type_to_line(g_gicc_base, type);
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#else
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#error "Invalid ARM GIC architecture version specified for platform port"
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#endif /* ARM_GIC_ARCH */
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}
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#if ARM_GIC_ARCH == 2
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/*******************************************************************************
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* This function returns the type of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t arm_gic_get_pending_interrupt_type(void)
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{
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uint32_t id;
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assert(g_gicc_base);
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id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
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/* Assume that all secure interrupts are S-EL1 interrupts */
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if (id < 1022)
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return INTR_TYPE_S_EL1;
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if (id == GIC_SPURIOUS_INTERRUPT)
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return INTR_TYPE_INVAL;
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return INTR_TYPE_NS;
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}
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/*******************************************************************************
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* This function returns the id of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t arm_gic_get_pending_interrupt_id(void)
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{
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uint32_t id;
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assert(g_gicc_base);
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id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
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if (id < 1022)
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return id;
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if (id == 1023)
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return INTR_ID_UNAVAILABLE;
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/*
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* Find out which non-secure interrupt it is under the assumption that
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* the GICC_CTLR.AckCtl bit is 0.
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*/
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return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK;
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}
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/*******************************************************************************
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* This functions reads the GIC cpu interface Interrupt Acknowledge register
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* to start handling the pending interrupt. It returns the contents of the IAR.
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******************************************************************************/
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uint32_t arm_gic_acknowledge_interrupt(void)
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{
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assert(g_gicc_base);
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return gicc_read_IAR(g_gicc_base);
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}
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/*******************************************************************************
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* This functions writes the GIC cpu interface End Of Interrupt register with
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* the passed value to finish handling the active interrupt
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******************************************************************************/
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void arm_gic_end_of_interrupt(uint32_t id)
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{
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assert(g_gicc_base);
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gicc_write_EOIR(g_gicc_base, id);
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}
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/*******************************************************************************
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* This function returns the type of the interrupt id depending upon the group
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* this interrupt has been configured under by the interrupt controller i.e.
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* group0 or group1.
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******************************************************************************/
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uint32_t arm_gic_get_interrupt_type(uint32_t id)
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{
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uint32_t group;
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assert(g_gicd_base);
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group = gicd_get_igroupr(g_gicd_base, id);
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/* Assume that all secure interrupts are S-EL1 interrupts */
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if (group == GRP0)
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return INTR_TYPE_S_EL1;
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else
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return INTR_TYPE_NS;
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}
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#else
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#error "Invalid ARM GIC architecture version specified for platform port"
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#endif /* ARM_GIC_ARCH */
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