124 lines
3.2 KiB
C
124 lines
3.2 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __GICV2_PRIVATE_H__
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#define __GICV2_PRIVATE_H__
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#include <gicv2.h>
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#include <mmio.h>
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#include <stdint.h>
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/*******************************************************************************
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* Private function prototypes
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******************************************************************************/
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void gicv2_spis_configure_defaults(uintptr_t gicd_base);
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void gicv2_secure_spis_configure(uintptr_t gicd_base,
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unsigned int num_ints,
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const unsigned int *sec_intr_list);
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void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
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unsigned int num_ints,
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const unsigned int *sec_intr_list);
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unsigned int gicv2_get_cpuif_id(uintptr_t base);
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/*******************************************************************************
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* GIC Distributor interface accessors for reading entire registers
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******************************************************************************/
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static inline unsigned int gicd_read_pidr2(uintptr_t base)
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{
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return mmio_read_32(base + GICD_PIDR2_GICV2);
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}
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/*******************************************************************************
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* GIC CPU interface accessors for reading entire registers
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******************************************************************************/
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static inline unsigned int gicc_read_ctlr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_CTLR);
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}
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static inline unsigned int gicc_read_pmr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_PMR);
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}
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static inline unsigned int gicc_read_BPR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_BPR);
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}
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static inline unsigned int gicc_read_IAR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_IAR);
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}
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static inline unsigned int gicc_read_EOIR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_EOIR);
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}
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static inline unsigned int gicc_read_hppir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_HPPIR);
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}
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static inline unsigned int gicc_read_ahppir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_AHPPIR);
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}
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static inline unsigned int gicc_read_dir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_DIR);
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}
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static inline unsigned int gicc_read_iidr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_IIDR);
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}
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/*******************************************************************************
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* GIC CPU interface accessors for writing entire registers
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******************************************************************************/
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static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_CTLR, val);
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}
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static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_PMR, val);
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}
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static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_BPR, val);
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}
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static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_IAR, val);
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}
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static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_EOIR, val);
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}
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static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_HPPIR, val);
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}
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static inline void gicc_write_dir(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_DIR, val);
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}
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#endif /* __GICV2_PRIVATE_H__ */
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