512 lines
18 KiB
C
512 lines
18 KiB
C
/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <platform.h>
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#include <string.h>
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#include "psci_private.h"
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/*
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* SPD power management operations, expected to be supplied by the registered
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* SPD on successful SP initialization
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*/
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const spd_pm_ops_t *psci_spd_pm;
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/*******************************************************************************
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* Arrays that hold the platform's power domain tree information for state
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* management of power domains.
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* Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain
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* which is an ancestor of a CPU power domain.
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* Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain
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******************************************************************************/
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non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]
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#if USE_COHERENT_MEM
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__attribute__ ((section("tzfw_coherent_mem")))
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#endif
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;
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cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* Pointer to functions exported by the platform to complete power mgmt. ops
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******************************************************************************/
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const plat_pm_ops_t *psci_plat_pm_ops;
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/*******************************************************************************
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* Check that the maximum power level supported by the platform makes sense
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* ****************************************************************************/
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CASSERT(PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL && \
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PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL, \
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assert_platform_max_pwrlvl_check);
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/*******************************************************************************
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* This function is passed a cpu_index and the highest level in the topology
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* tree. It iterates through the nodes to find the highest power level at which
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* a domain is physically powered off.
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******************************************************************************/
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uint32_t psci_find_max_phys_off_pwrlvl(uint32_t end_pwrlvl,
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unsigned int cpu_idx)
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{
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int max_pwrlvl, level;
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unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
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if (psci_get_phys_state(cpu_idx, PSCI_CPU_PWR_LVL) != PSCI_STATE_OFF)
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return PSCI_INVALID_DATA;
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max_pwrlvl = PSCI_CPU_PWR_LVL;
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for (level = PSCI_CPU_PWR_LVL + 1; level <= end_pwrlvl; level++) {
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if (psci_get_phys_state(parent_idx, level) == PSCI_STATE_OFF)
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max_pwrlvl = level;
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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}
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return max_pwrlvl;
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}
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/*******************************************************************************
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* This function verifies that the all the other cores in the system have been
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* turned OFF and the current CPU is the last running CPU in the system.
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* Returns 1 (true) if the current CPU is the last ON CPU or 0 (false)
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* otherwise.
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******************************************************************************/
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unsigned int psci_is_last_on_cpu(void)
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{
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unsigned long mpidr = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
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unsigned int i;
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for (i = 0; i < PLATFORM_CORE_COUNT; i++) {
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if (psci_cpu_pd_nodes[i].mpidr == mpidr) {
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assert(psci_get_state(i, PSCI_CPU_PWR_LVL)
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== PSCI_STATE_ON);
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continue;
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}
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if (psci_get_state(i, PSCI_CPU_PWR_LVL) != PSCI_STATE_OFF)
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return 0;
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}
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return 1;
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}
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/*******************************************************************************
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* Routine to return the maximum power level to traverse to after a cpu has
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* been physically powered up. It is expected to be called immediately after
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* reset from assembler code.
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******************************************************************************/
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int get_power_on_target_pwrlvl(void)
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{
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int pwrlvl;
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#if DEBUG
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unsigned int state;
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/*
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* Sanity check the state of the cpu. It should be either suspend or "on
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* pending"
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*/
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state = psci_get_state(plat_my_core_pos(), PSCI_CPU_PWR_LVL);
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assert(state == PSCI_STATE_SUSPEND || state == PSCI_STATE_ON_PENDING);
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#endif
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/*
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* Assume that this cpu was suspended and retrieve its target power
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* level. If it is invalid then it could only have been turned off
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* earlier. PLAT_MAX_PWR_LVL will be the highest power level a
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* cpu can be turned off to.
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*/
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pwrlvl = psci_get_suspend_pwrlvl();
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if (pwrlvl == PSCI_INVALID_DATA)
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pwrlvl = PLAT_MAX_PWR_LVL;
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return pwrlvl;
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}
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/*******************************************************************************
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* PSCI helper function to get the parent nodes corresponding to a cpu_index.
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******************************************************************************/
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void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
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int end_lvl,
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unsigned int node_index[])
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{
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unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node;
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int i;
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for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) {
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*node_index++ = parent_node;
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parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node;
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}
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}
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/*******************************************************************************
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* This function is passed a cpu_index and the highest level in the topology
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* tree and the state which each node should transition to. It updates the
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* state of each node between the specified power levels.
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******************************************************************************/
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void psci_do_state_coordination(int end_pwrlvl,
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unsigned int cpu_idx,
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uint32_t state)
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{
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int level;
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unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
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psci_set_state(cpu_idx, state, PSCI_CPU_PWR_LVL);
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for (level = PSCI_CPU_PWR_LVL + 1; level <= end_pwrlvl; level++) {
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psci_set_state(parent_idx, state, level);
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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}
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}
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/*******************************************************************************
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* This function is passed a cpu_index and the highest level in the topology
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* tree that the operation should be applied to. It picks up locks in order of
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* increasing power domain level in the range specified.
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******************************************************************************/
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void psci_acquire_pwr_domain_locks(int end_pwrlvl, unsigned int cpu_idx)
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{
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unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
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int level;
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/* No locking required for level 0. Hence start locking from level 1 */
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for (level = PSCI_CPU_PWR_LVL + 1; level <= end_pwrlvl; level++) {
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psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]);
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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}
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}
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/*******************************************************************************
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* This function is passed a cpu_index and the highest level in the topology
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* tree that the operation should be applied to. It releases the locks in order
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* of decreasing power domain level in the range specified.
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******************************************************************************/
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void psci_release_pwr_domain_locks(int end_pwrlvl, unsigned int cpu_idx)
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{
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unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0};
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int level;
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/* Get the parent nodes */
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psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
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/* Unlock top down. No unlocking required for level 0. */
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for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1; level--) {
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parent_idx = parent_nodes[level - 1];
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psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]);
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}
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}
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/*******************************************************************************
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* Simple routine to determine whether a mpidr is valid or not.
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******************************************************************************/
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int psci_validate_mpidr(unsigned long mpidr)
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{
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if (plat_core_pos_by_mpidr(mpidr) < 0)
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return PSCI_E_INVALID_PARAMS;
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* This function determines the full entrypoint information for the requested
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* PSCI entrypoint on power on/resume and returns it.
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******************************************************************************/
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int psci_get_ns_ep_info(entry_point_info_t *ep,
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uint64_t entrypoint, uint64_t context_id)
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{
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uint32_t ep_attr, mode, sctlr, daif, ee;
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uint32_t ns_scr_el3 = read_scr_el3();
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uint32_t ns_sctlr_el1 = read_sctlr_el1();
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sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1;
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ee = 0;
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ep_attr = NON_SECURE | EP_ST_DISABLE;
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if (sctlr & SCTLR_EE_BIT) {
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ep_attr |= EP_EE_BIG;
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ee = 1;
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}
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SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
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ep->pc = entrypoint;
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memset(&ep->args, 0, sizeof(ep->args));
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ep->args.arg0 = context_id;
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/*
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* Figure out whether the cpu enters the non-secure address space
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* in aarch32 or aarch64
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*/
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if (ns_scr_el3 & SCR_RW_BIT) {
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/*
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* Check whether a Thumb entry point has been provided for an
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* aarch64 EL
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*/
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if (entrypoint & 0x1)
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return PSCI_E_INVALID_PARAMS;
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mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1;
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ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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} else {
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mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
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/*
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* TODO: Choose async. exception bits if HYP mode is not
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* implemented according to the values of SCR.{AW, FW} bits
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*/
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daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
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ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif);
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* This function takes an index and level of a power domain node in the topology
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* tree and returns its state. State of a non-leaf node needs to be calculated.
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******************************************************************************/
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unsigned short psci_get_state(unsigned int idx,
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int level)
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{
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/* A cpu node just contains the state which can be directly returned */
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if (level == PSCI_CPU_PWR_LVL) {
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flush_cpu_data_by_index(idx, psci_svc_cpu_data.psci_state);
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return get_cpu_data_by_index(idx, psci_svc_cpu_data.psci_state);
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}
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#if !USE_COHERENT_MEM
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flush_dcache_range((uint64_t) &psci_non_cpu_pd_nodes[idx],
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sizeof(psci_non_cpu_pd_nodes[idx]));
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#endif
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/*
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* For a power level higher than a cpu, the state has to be
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* calculated. It depends upon the value of the reference count
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* which is managed by each node at the next lower power level
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* e.g. for a cluster, each cpu increments/decrements the reference
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* count. If the reference count is 0 then the power level is
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* OFF else ON.
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*/
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if (psci_non_cpu_pd_nodes[idx].ref_count)
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return PSCI_STATE_ON;
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else
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return PSCI_STATE_OFF;
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}
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/*******************************************************************************
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* This function takes an index and level of a power domain node in the topology
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* tree and a target state. State of a non-leaf node needs to be converted to
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* a reference count. State of a leaf node can be set directly.
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******************************************************************************/
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void psci_set_state(unsigned int idx,
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unsigned short state,
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int level)
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{
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/*
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* For a power level higher than a cpu, the state is used
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* to decide whether the reference count is incremented or
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* decremented. Entry into the ON_PENDING state does not have
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* effect.
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*/
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if (level > PSCI_CPU_PWR_LVL) {
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switch (state) {
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case PSCI_STATE_ON:
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psci_non_cpu_pd_nodes[idx].ref_count++;
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break;
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case PSCI_STATE_OFF:
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case PSCI_STATE_SUSPEND:
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psci_non_cpu_pd_nodes[idx].ref_count--;
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break;
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case PSCI_STATE_ON_PENDING:
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/*
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* A power level higher than a cpu will not undergo
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* a state change when it is about to be turned on
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*/
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return;
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default:
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assert(0);
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#if !USE_COHERENT_MEM
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flush_dcache_range((uint64_t) &psci_non_cpu_pd_nodes[idx],
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sizeof(psci_non_cpu_pd_nodes[idx]));
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#endif
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}
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} else {
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set_cpu_data_by_index(idx, psci_svc_cpu_data.psci_state, state);
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flush_cpu_data_by_index(idx, psci_svc_cpu_data.psci_state);
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}
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}
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/*******************************************************************************
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* A power domain could be on, on_pending, suspended or off. These are the
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* logical states it can be in. Physically either it is off or on. When it is in
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* the state on_pending then it is about to be turned on. It is not possible to
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* tell whether that's actually happened or not. So we err on the side of
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* caution & treat the power domain as being turned off.
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******************************************************************************/
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unsigned short psci_get_phys_state(unsigned int idx,
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int level)
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{
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unsigned int state;
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state = psci_get_state(idx, level);
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return get_phys_state(state);
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}
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/*******************************************************************************
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* Generic handler which is called when a cpu is physically powered on. It
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* traverses the node information and finds the highest power level powered
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* off and performs generic, architectural, platform setup and state management
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* to power on that power level and power levels below it.
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* e.g. For a cpu that's been powered on, it will call the platform specific
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* code to enable the gic cpu interface and for a cluster it will enable
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* coherency at the interconnect level in addition to gic cpu interface.
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******************************************************************************/
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void psci_power_up_finish(int end_pwrlvl,
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pwrlvl_power_on_finisher_t pon_handler)
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{
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unsigned int cpu_idx = plat_my_core_pos();
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unsigned int max_phys_off_pwrlvl;
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/*
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* This function acquires the lock corresponding to each power
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* level so that by the time all locks are taken, the system topology
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* is snapshot and state management can be done safely.
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*/
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psci_acquire_pwr_domain_locks(end_pwrlvl,
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cpu_idx);
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max_phys_off_pwrlvl = psci_find_max_phys_off_pwrlvl(end_pwrlvl,
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cpu_idx);
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assert(max_phys_off_pwrlvl != PSCI_INVALID_DATA);
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/* Perform generic, architecture and platform specific handling */
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pon_handler(cpu_idx, max_phys_off_pwrlvl);
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/*
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* This function updates the state of each power instance
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* corresponding to the cpu index in the range of power levels
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* specified.
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*/
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psci_do_state_coordination(end_pwrlvl,
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cpu_idx,
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PSCI_STATE_ON);
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/*
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* This loop releases the lock corresponding to each power level
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* in the reverse order to which they were acquired.
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*/
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psci_release_pwr_domain_locks(end_pwrlvl,
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cpu_idx);
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}
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/*******************************************************************************
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* This function initializes the set of hooks that PSCI invokes as part of power
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* management operation. The power management hooks are expected to be provided
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* by the SPD, after it finishes all its initialization
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******************************************************************************/
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void psci_register_spd_pm_hook(const spd_pm_ops_t *pm)
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{
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assert(pm);
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psci_spd_pm = pm;
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if (pm->svc_migrate)
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psci_caps |= define_psci_cap(PSCI_MIG_AARCH64);
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if (pm->svc_migrate_info)
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psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64)
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| define_psci_cap(PSCI_MIG_INFO_TYPE);
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}
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/*******************************************************************************
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* This function invokes the migrate info hook in the spd_pm_ops. It performs
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* the necessary return value validation. If the Secure Payload is UP and
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* migrate capable, it returns the mpidr of the CPU on which the Secure payload
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* is resident through the mpidr parameter. Else the value of the parameter on
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* return is undefined.
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******************************************************************************/
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int psci_spd_migrate_info(uint64_t *mpidr)
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{
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int rc;
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if (!psci_spd_pm || !psci_spd_pm->svc_migrate_info)
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return PSCI_E_NOT_SUPPORTED;
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rc = psci_spd_pm->svc_migrate_info(mpidr);
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assert(rc == PSCI_TOS_UP_MIG_CAP || rc == PSCI_TOS_NOT_UP_MIG_CAP \
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|| rc == PSCI_TOS_NOT_PRESENT_MP || rc == PSCI_E_NOT_SUPPORTED);
|
|
|
|
return rc;
|
|
}
|
|
|
|
|
|
/*******************************************************************************
|
|
* This function prints the state of all power domains present in the
|
|
* system
|
|
******************************************************************************/
|
|
void psci_print_power_domain_map(void)
|
|
{
|
|
#if LOG_LEVEL >= LOG_LEVEL_INFO
|
|
unsigned int idx, state;
|
|
|
|
/* This array maps to the PSCI_STATE_X definitions in psci.h */
|
|
static const char *psci_state_str[] = {
|
|
"ON",
|
|
"OFF",
|
|
"ON_PENDING",
|
|
"SUSPEND"
|
|
};
|
|
|
|
INFO("PSCI Power Domain Map:\n");
|
|
for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT); idx++) {
|
|
state = psci_get_state(idx, psci_non_cpu_pd_nodes[idx].level);
|
|
INFO(" Domain Node : Level %u, parent_node %d, State %s\n",
|
|
psci_non_cpu_pd_nodes[idx].level,
|
|
psci_non_cpu_pd_nodes[idx].parent_node,
|
|
psci_state_str[state]);
|
|
}
|
|
|
|
for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) {
|
|
state = psci_get_state(idx, PSCI_CPU_PWR_LVL);
|
|
INFO(" CPU Node : MPID 0x%lx, parent_node %d, State %s\n",
|
|
psci_cpu_pd_nodes[idx].mpidr,
|
|
psci_cpu_pd_nodes[idx].parent_node,
|
|
psci_state_str[state]);
|
|
}
|
|
#endif
|
|
}
|