264 lines
7.3 KiB
ArmAsm
264 lines
7.3 KiB
ArmAsm
/*
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* Copyright (c) 2015-2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#include <cortex_a72.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <platform_def.h>
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.globl plat_reset_handler
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.globl platform_get_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl platform_mem_init
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.globl platform_check_mpidr
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl plat_disable_acp
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl platform_is_primary_cpu
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.globl plat_brcm_calc_core_pos
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.globl plat_get_my_entrypoint
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/* ------------------------------------------------------------
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* void plat_l2_init(void);
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*
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* BL1 and BL2 run with one core, one cluster
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* This is safe to disable cluster coherency
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* to make use of the data cache MMU WB attribute
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* for the SRAM.
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*
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* Set L2 Auxiliary Control Register
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* --------------------------------------------------------------------
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*/
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func plat_l2_init
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mrs x0, CORTEX_A72_L2ACTLR_EL1
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#if (IMAGE_BL1 || IMAGE_BL2) || defined(USE_SINGLE_CLUSTER)
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orr x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI
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#else
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bic x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI
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#endif
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msr CORTEX_A72_L2ACTLR_EL1, x0
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/* Set L2 Control Register */
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mrs x0, CORTEX_A72_L2CTLR_EL1
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mov x1, #((CORTEX_A72_L2_DATA_RAM_LATENCY_MASK << \
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CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(CORTEX_A72_L2_TAG_RAM_LATENCY_MASK << \
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CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT) | \
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(U(0x1) << CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) | \
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(U(0x1) << CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT))
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bic x0, x0, x1
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mov x1, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
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CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(U(0x1) << CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) | \
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(U(0x1) << CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT))
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orr x0, x0, x1
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msr CORTEX_A72_L2CTLR_EL1, x0
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isb
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ret
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endfunc plat_l2_init
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/* --------------------------------------------------------------------
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* void plat_reset_handler(void);
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*
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* Before adding code in this function, refer to the guidelines in
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* docs/firmware-design.md.
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*
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* --------------------------------------------------------------------
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*/
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func plat_reset_handler
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mov x9, x30
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bl plat_l2_init
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mov x30, x9
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ret
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endfunc plat_reset_handler
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/* -----------------------------------------------------
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* void platform_get_entrypoint (unsigned int mpid);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot.
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* On a cold boot the secondaries first wait for the
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* platform to be initialized after which they are
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* hotplugged in. The primary proceeds to perform the
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* platform initialization.
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* -----------------------------------------------------
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*/
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func platform_get_entrypoint
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/*TBD-STINGRAY*/
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mov x0, #0
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ret
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endfunc platform_get_entrypoint
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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bl plat_my_core_pos
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mov_imm x1, SECONDARY_CPU_SPIN_BASE_ADDR
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add x0, x1, x0, LSL #3
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mov x1, #0
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str x1, [x0]
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/* Wait until the entrypoint gets populated */
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poll_mailbox:
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ldr x1, [x0]
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cbz x1, 1f
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br x1
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1:
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wfe
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b poll_mailbox
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endfunc plat_secondary_cold_boot_setup
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/* -----------------------------------------------------
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* void platform_mem_init(void);
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*
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* We don't need to carry out any memory initialization
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* on CSS platforms. The Secure RAM is accessible straight away.
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* -----------------------------------------------------
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*/
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func platform_mem_init
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/*TBD-STINGRAY*/
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ret
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endfunc platform_mem_init
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/* -----------------------------------------------------
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* Placeholder function which should be redefined by
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* each platform.
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* -----------------------------------------------------
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*/
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func platform_check_mpidr
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/*TBD-STINGRAY*/
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mov x0, xzr
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ret
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endfunc platform_check_mpidr
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, BRCM_CRASH_CONSOLE_BASE
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mov_imm x1, BRCM_CRASH_CONSOLE_REFCLK
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mov_imm x2, BRCM_CRASH_CONSOLE_BAUDRATE
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b console_16550_core_init
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ret
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2, x3
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, BRCM_CRASH_CONSOLE_BASE
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b console_16550_core_putc
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ret
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush(void)
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* Function to flush crash console
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, BRCM_CRASH_CONSOLE_BASE
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b console_16550_core_flush
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ret
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endfunc plat_crash_console_flush
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/* -----------------------------------------------------
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* Placeholder function which should be redefined by
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* each platform. This function is allowed to use
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* registers x0 - x17.
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* -----------------------------------------------------
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*/
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func plat_disable_acp
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/*TBD-STINGRAY*/
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ret
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endfunc plat_disable_acp
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu (applicable only after a cold boot)
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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b platform_is_primary_cpu
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_brcm_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_brcm_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int platform_is_primary_cpu (void);
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*
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* Find out whether the current cpu is the primary
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* cpu (applicable only after a cold boot)
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* -----------------------------------------------------
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*/
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func platform_is_primary_cpu
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mov x9, x30
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bl plat_my_core_pos
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cmp x0, #PRIMARY_CPU
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cset x0, eq
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ret x9
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endfunc platform_is_primary_cpu
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/* -----------------------------------------------------
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* unsigned int plat_brcm_calc_core_pos(uint64_t mpidr)
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* Helper function to calculate the core position.
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* With this function: CorePos = (ClusterId * 4) +
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* CoreId
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* -----------------------------------------------------
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*/
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func plat_brcm_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #7
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ret
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endfunc plat_brcm_calc_core_pos
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func plat_get_my_entrypoint
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mrs x0, mpidr_el1
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b platform_get_entrypoint
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endfunc plat_get_my_entrypoint
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