Varun Wadekar d439cea9e8 locks: bakery: add a DMB to the 'read_cache_op' macro ... ARM has a weak memory ordering model. This means that without explicit barriers, memory accesses can be observed differently than program order. In this case, the cache invalidate instruction can be observed after the subsequent read to address. To solve this, a DMB instruction is required between the cache invalidate and the read. This ensures that the cache invalidate completes before all memory accesses in program order after the DMB. This patch updates the 'read_cache_op' macro to issue a DMB after the cache invalidate instruction to fix this anomaly. Change-Id: Iac9a90d228c57ba8bcdca7e409ea6719546ab441 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2020-03-06 08:53:33 -08:00
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bakery	locks: bakery: add a DMB to the 'read_cache_op' macro	2020-03-06 08:53:33 -08:00
exclusive	Fix the CAS spinlock implementation	2019-10-04 10:19:35 +02:00