347 lines
7.5 KiB
C
347 lines
7.5 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mt_spm.h>
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#include <mt_spm_conservation.h>
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#include <mt_spm_idle.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_reg.h>
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#include <mt_spm_resource_req.h>
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#include <plat_pm.h>
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#define __WAKE_SRC_FOR_IDLE_COMMON__ \
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(R12_PCM_TIMER | \
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R12_KP_IRQ_B | \
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R12_APWDT_EVENT_B | \
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R12_APXGPT1_EVENT_B | \
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R12_CONN2AP_SPM_WAKEUP_B | \
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R12_EINT_EVENT_B | \
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R12_CONN_WDT_IRQ_B | \
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R12_CCIF0_EVENT_B | \
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R12_SSPM2SPM_WAKEUP_B | \
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R12_SCP2SPM_WAKEUP_B | \
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R12_ADSP2SPM_WAKEUP_B | \
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R12_USBX_CDSC_B | \
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R12_USBX_POWERDWN_B | \
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R12_SYS_TIMER_EVENT_B | \
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R12_EINT_EVENT_SECURE_B | \
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R12_AFE_IRQ_MCU_B | \
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R12_SYS_CIRQ_IRQ_B | \
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R12_MD2AP_PEER_EVENT_B | \
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R12_MD1_WDT_B | \
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R12_CLDMA_EVENT_B | \
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R12_REG_CPU_WAKEUP | \
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R12_APUSYS_WAKE_HOST_B)
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#if defined(CFG_MICROTRUST_TEE_SUPPORT)
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#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
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#else
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#define WAKE_SRC_FOR_IDLE \
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(__WAKE_SRC_FOR_IDLE_COMMON__ | \
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R12_SEJ_EVENT_B)
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#endif
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static struct pwr_ctrl idle_spm_pwr = {
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.wake_src = WAKE_SRC_FOR_IDLE,
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/* SPM_AP_STANDBY_CON */
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/* [0] */
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.reg_wfi_op = 0,
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/* [1] */
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.reg_wfi_type = 0,
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/* [2] */
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.reg_mp0_cputop_idle_mask = 0,
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/* [3] */
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.reg_mp1_cputop_idle_mask = 0,
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/* [4] */
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.reg_mcusys_idle_mask = 0,
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/* [25] */
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.reg_md_apsrc_1_sel = 0,
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/* [26] */
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.reg_md_apsrc_0_sel = 0,
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/* [29] */
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.reg_conn_apsrc_sel = 0,
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/* SPM_SRC_REQ */
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/* [0] */
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.reg_spm_apsrc_req = 0,
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/* [1] */
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.reg_spm_f26m_req = 1,
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/* [3] */
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.reg_spm_infra_req = 1,
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/* [4] */
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.reg_spm_vrf18_req = 0,
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/* [7] FIXME: default disable HW Auto S1 */
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.reg_spm_ddr_en_req = 1,
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/* [8] */
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.reg_spm_dvfs_req = 0,
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/* [9] */
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.reg_spm_sw_mailbox_req = 0,
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/* [10] */
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.reg_spm_sspm_mailbox_req = 0,
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/* [11] */
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.reg_spm_adsp_mailbox_req = 0,
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/* [12] */
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.reg_spm_scp_mailbox_req = 0,
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/* SPM_SRC_MASK */
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/* [0] */
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.reg_sspm_srcclkena_0_mask_b = 1,
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/* [1] */
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.reg_sspm_infra_req_0_mask_b = 1,
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/* [2] */
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.reg_sspm_apsrc_req_0_mask_b = 1,
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/* [3] */
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.reg_sspm_vrf18_req_0_mask_b = 1,
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/* [4] */
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.reg_sspm_ddr_en_0_mask_b = 1,
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/* [5] */
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.reg_scp_srcclkena_mask_b = 1,
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/* [6] */
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.reg_scp_infra_req_mask_b = 1,
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/* [7] */
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.reg_scp_apsrc_req_mask_b = 1,
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/* [8] */
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.reg_scp_vrf18_req_mask_b = 1,
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/* [9] */
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.reg_scp_ddr_en_mask_b = 1,
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/* [10] */
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.reg_audio_dsp_srcclkena_mask_b = 1,
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/* [11] */
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.reg_audio_dsp_infra_req_mask_b = 1,
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/* [12] */
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.reg_audio_dsp_apsrc_req_mask_b = 1,
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/* [13] */
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.reg_audio_dsp_vrf18_req_mask_b = 1,
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/* [14] */
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.reg_audio_dsp_ddr_en_mask_b = 1,
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/* [15] */
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.reg_apu_srcclkena_mask_b = 1,
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/* [16] */
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.reg_apu_infra_req_mask_b = 1,
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/* [17] */
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.reg_apu_apsrc_req_mask_b = 1,
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/* [18] */
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.reg_apu_vrf18_req_mask_b = 1,
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/* [19] */
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.reg_apu_ddr_en_mask_b = 1,
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/* [20] */
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.reg_cpueb_srcclkena_mask_b = 1,
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/* [21] */
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.reg_cpueb_infra_req_mask_b = 1,
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/* [22] */
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.reg_cpueb_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_cpueb_vrf18_req_mask_b = 1,
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/* [24] */
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.reg_cpueb_ddr_en_mask_b = 1,
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/* [25] */
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.reg_bak_psri_srcclkena_mask_b = 0,
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/* [26] */
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.reg_bak_psri_infra_req_mask_b = 0,
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/* [27] */
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.reg_bak_psri_apsrc_req_mask_b = 0,
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/* [28] */
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.reg_bak_psri_vrf18_req_mask_b = 0,
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/* [29] */
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.reg_bak_psri_ddr_en_mask_b = 0,
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/* SPM_SRC2_MASK */
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/* [0] */
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.reg_msdc0_srcclkena_mask_b = 1,
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/* [1] */
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.reg_msdc0_infra_req_mask_b = 1,
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/* [2] */
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.reg_msdc0_apsrc_req_mask_b = 1,
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/* [3] */
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.reg_msdc0_vrf18_req_mask_b = 1,
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/* [4] */
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.reg_msdc0_ddr_en_mask_b = 1,
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/* [5] */
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.reg_msdc1_srcclkena_mask_b = 1,
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/* [6] */
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.reg_msdc1_infra_req_mask_b = 1,
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/* [7] */
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.reg_msdc1_apsrc_req_mask_b = 1,
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/* [8] */
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.reg_msdc1_vrf18_req_mask_b = 1,
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/* [9] */
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.reg_msdc1_ddr_en_mask_b = 1,
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/* [10] */
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.reg_msdc2_srcclkena_mask_b = 1,
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/* [11] */
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.reg_msdc2_infra_req_mask_b = 1,
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/* [12] */
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.reg_msdc2_apsrc_req_mask_b = 1,
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/* [13] */
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.reg_msdc2_vrf18_req_mask_b = 1,
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/* [14] */
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.reg_msdc2_ddr_en_mask_b = 1,
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/* [15] */
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.reg_ufs_srcclkena_mask_b = 1,
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/* [16] */
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.reg_ufs_infra_req_mask_b = 1,
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/* [17] */
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.reg_ufs_apsrc_req_mask_b = 1,
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/* [18] */
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.reg_ufs_vrf18_req_mask_b = 1,
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/* [19] */
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.reg_ufs_ddr_en_mask_b = 1,
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/* [20] */
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.reg_usb_srcclkena_mask_b = 1,
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/* [21] */
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.reg_usb_infra_req_mask_b = 1,
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/* [22] */
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.reg_usb_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_usb_vrf18_req_mask_b = 1,
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/* [24] */
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.reg_usb_ddr_en_mask_b = 1,
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/* [25] */
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.reg_pextp_p0_srcclkena_mask_b = 1,
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/* [26] */
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.reg_pextp_p0_infra_req_mask_b = 1,
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/* [27] */
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.reg_pextp_p0_apsrc_req_mask_b = 1,
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/* [28] */
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.reg_pextp_p0_vrf18_req_mask_b = 1,
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/* [29] */
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.reg_pextp_p0_ddr_en_mask_b = 1,
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/* SPM_SRC3_MASK */
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/* [0] */
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.reg_pextp_p1_srcclkena_mask_b = 1,
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/* [1] */
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.reg_pextp_p1_infra_req_mask_b = 1,
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/* [2] */
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.reg_pextp_p1_apsrc_req_mask_b = 1,
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/* [3] */
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.reg_pextp_p1_vrf18_req_mask_b = 1,
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/* [4] */
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.reg_pextp_p1_ddr_en_mask_b = 1,
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/* [5] */
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.reg_gce0_infra_req_mask_b = 1,
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/* [6] */
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.reg_gce0_apsrc_req_mask_b = 1,
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/* [7] */
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.reg_gce0_vrf18_req_mask_b = 1,
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/* [8] */
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.reg_gce0_ddr_en_mask_b = 1,
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/* [9] */
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.reg_gce1_infra_req_mask_b = 1,
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/* [10] */
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.reg_gce1_apsrc_req_mask_b = 1,
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/* [11] */
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.reg_gce1_vrf18_req_mask_b = 1,
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/* [12] */
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.reg_gce1_ddr_en_mask_b = 1,
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/* [13] */
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.reg_spm_srcclkena_reserved_mask_b = 1,
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/* [14] */
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.reg_spm_infra_req_reserved_mask_b = 1,
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/* [15] */
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.reg_spm_apsrc_req_reserved_mask_b = 1,
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/* [16] */
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.reg_spm_vrf18_req_reserved_mask_b = 1,
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/* [17] */
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.reg_spm_ddr_en_reserved_mask_b = 1,
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/* [18] */
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.reg_disp0_apsrc_req_mask_b = 1,
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/* [19] */
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.reg_disp0_ddr_en_mask_b = 1,
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/* [20] */
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.reg_disp1_apsrc_req_mask_b = 1,
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/* [21] */
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.reg_disp1_ddr_en_mask_b = 1,
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/* [22] */
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.reg_disp2_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_disp2_ddr_en_mask_b = 1,
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/* [24] */
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.reg_disp3_apsrc_req_mask_b = 1,
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/* [25] */
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.reg_disp3_ddr_en_mask_b = 1,
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/* [26] */
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.reg_infrasys_apsrc_req_mask_b = 0,
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/* [27] */
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.reg_infrasys_ddr_en_mask_b = 1,
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/* [28] */
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.reg_cg_check_srcclkena_mask_b = 1,
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/* [29] */
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.reg_cg_check_apsrc_req_mask_b = 1,
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/* [30] */
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.reg_cg_check_vrf18_req_mask_b = 1,
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/* [31] */
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.reg_cg_check_ddr_en_mask_b = 1,
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/* SPM_SRC4_MASK */
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/* [8:0] */
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.reg_mcusys_merge_apsrc_req_mask_b = 0x17,
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/* [17:9] */
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.reg_mcusys_merge_ddr_en_mask_b = 0x17,
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/* [19:18] */
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.reg_dramc_md32_infra_req_mask_b = 0,
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/* [21:20] */
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.reg_dramc_md32_vrf18_req_mask_b = 0,
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/* [23:22] */
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.reg_dramc_md32_ddr_en_mask_b = 0,
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/* [24] */
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.reg_dvfsrc_event_trigger_mask_b = 1,
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/* SPM_WAKEUP_EVENT_MASK2 */
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/* [3:0] */
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.reg_sc_sw2spm_wakeup_mask_b = 0,
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/* [4] */
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.reg_sc_adsp2spm_wakeup_mask_b = 0,
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/* [8:5] */
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.reg_sc_sspm2spm_wakeup_mask_b = 0,
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/* [9] */
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.reg_sc_scp2spm_wakeup_mask_b = 0,
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/* [10] */
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.reg_csyspwrup_ack_mask = 0,
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/* [11] */
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.reg_csyspwrup_req_mask = 1,
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/* SPM_WAKEUP_EVENT_MASK */
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/* [31:0] */
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.reg_wakeup_event_mask = 0xC1282203,
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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/* [31:0] */
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.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
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};
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struct spm_lp_scen idle_spm_lp = {
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.pwrctrl = &idle_spm_pwr,
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};
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int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
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spm_idle_conduct fn)
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{
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unsigned int src_req = 0;
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if (fn != NULL) {
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fn(&idle_spm_lp, &src_req);
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}
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return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
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}
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void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
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struct wake_status **status)
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{
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spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
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}
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void mt_spm_idle_generic_init(void)
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{
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spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
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}
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