527 lines
12 KiB
C
527 lines
12 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <string.h>
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#include <common/debug.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <mt_spm.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_pmic_wrap.h>
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#include <mt_spm_reg.h>
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#include <mt_spm_vcorefs.h>
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#include <mtk_plat_common.h>
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#include <mtk_sip_svc.h>
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#include <platform_def.h>
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#define VCORE_MAX_OPP 4
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#define DRAM_MAX_OPP 7
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static bool spm_dvfs_init_done;
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static bool dvfs_enable_done;
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static int vcore_opp_0_uv = 750000;
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static int vcore_opp_1_uv = 650000;
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static int vcore_opp_2_uv = 600000;
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static int vcore_opp_3_uv = 550000;
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static struct reg_config dvfsrc_init_configs[] = {
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{ DVFSRC_HRT_REQ_UNIT, 0x0000001E },
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{ DVFSRC_DEBOUNCE_TIME, 0x19651965 },
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{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
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{ DVFSRC_LEVEL_MASK, 0x000EE000 },
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{ DVFSRC_DDR_QOS0, 0x00000019 },
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{ DVFSRC_DDR_QOS1, 0x00000026 },
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{ DVFSRC_DDR_QOS2, 0x00000033 },
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{ DVFSRC_DDR_QOS3, 0x0000003B },
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{ DVFSRC_DDR_QOS4, 0x0000004C },
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{ DVFSRC_DDR_QOS5, 0x00000066 },
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{ DVFSRC_DDR_QOS6, 0x00660066 },
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{ DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
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{ DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
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{ DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
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{ DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
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{ DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
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{ DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
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{ DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
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{ DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
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{ DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
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{ DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
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{ DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
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{ DVFSRC_MD_LATENCY_IMPROVE, 0x00000040 },
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{ DVFSRC_DDR_REQUEST, 0x00004321 },
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{ DVFSRC_DDR_REQUEST3, 0x00000065 },
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{ DVFSRC_DDR_ADD_REQUEST, 0x66543210 },
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{ DVFSRC_HRT_REQUEST, 0x66654321 },
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{ DVFSRC_DDR_REQUEST5, 0x54321000 },
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{ DVFSRC_DDR_REQUEST7, 0x66000000 },
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{ DVFSRC_VCORE_USER_REQ, 0x00010A29 },
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{ DVFSRC_HRT_HIGH_3, 0x18A618A6 },
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{ DVFSRC_HRT_HIGH_2, 0x18A61183 },
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{ DVFSRC_HRT_HIGH_1, 0x0D690B80 },
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{ DVFSRC_HRT_HIGH, 0x070804B0 },
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{ DVFSRC_HRT_LOW_3, 0x18A518A5 },
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{ DVFSRC_HRT_LOW_2, 0x18A51182 },
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{ DVFSRC_HRT_LOW_1, 0x0D680B7F },
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{ DVFSRC_HRT_LOW, 0x070704AF },
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{ DVFSRC_BASIC_CONTROL_3, 0x00000006 },
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{ DVFSRC_INT_EN, 0x00000002 },
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{ DVFSRC_QOS_EN, 0x0000407C },
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{ DVFSRC_HRT_BW_BASE, 0x00000004 },
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{ DVFSRC_PCIE_VCORE_REQ, 0x65908101 },
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{ DVFSRC_CURRENT_FORCE, 0x00000001 },
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{ DVFSRC_BASIC_CONTROL, 0x6698444B },
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{ DVFSRC_BASIC_CONTROL, 0x6698054B },
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{ DVFSRC_CURRENT_FORCE, 0x00000000 },
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};
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static struct pwr_ctrl vcorefs_ctrl = {
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.wake_src = R12_REG_CPU_WAKEUP,
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/* default VCORE DVFS is disabled */
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.pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
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SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS),
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/* SPM_AP_STANDBY_CON */
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/* [0] */
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.reg_wfi_op = 0,
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/* [1] */
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.reg_wfi_type = 0,
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/* [2] */
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.reg_mp0_cputop_idle_mask = 0,
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/* [3] */
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.reg_mp1_cputop_idle_mask = 0,
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/* [4] */
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.reg_mcusys_idle_mask = 0,
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/* [25] */
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.reg_md_apsrc_1_sel = 0,
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/* [26] */
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.reg_md_apsrc_0_sel = 0,
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/* [29] */
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.reg_conn_apsrc_sel = 0,
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/* SPM_SRC_REQ */
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/* [0] */
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.reg_spm_apsrc_req = 0,
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/* [1] */
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.reg_spm_f26m_req = 0,
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/* [3] */
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.reg_spm_infra_req = 0,
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/* [4] */
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.reg_spm_vrf18_req = 0,
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/* [7] FIXME: default disable HW Auto S1*/
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.reg_spm_ddr_en_req = 1,
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/* [8] */
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.reg_spm_dvfs_req = 0,
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/* [9] */
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.reg_spm_sw_mailbox_req = 0,
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/* [10] */
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.reg_spm_sspm_mailbox_req = 0,
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/* [11] */
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.reg_spm_adsp_mailbox_req = 0,
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/* [12] */
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.reg_spm_scp_mailbox_req = 0,
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/* SPM_SRC_MASK */
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/* [0] */
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.reg_sspm_srcclkena_0_mask_b = 1,
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/* [1] */
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.reg_sspm_infra_req_0_mask_b = 1,
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/* [2] */
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.reg_sspm_apsrc_req_0_mask_b = 1,
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/* [3] */
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.reg_sspm_vrf18_req_0_mask_b = 1,
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/* [4] */
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.reg_sspm_ddr_en_0_mask_b = 1,
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/* [5] */
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.reg_scp_srcclkena_mask_b = 1,
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/* [6] */
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.reg_scp_infra_req_mask_b = 1,
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/* [7] */
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.reg_scp_apsrc_req_mask_b = 1,
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/* [8] */
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.reg_scp_vrf18_req_mask_b = 1,
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/* [9] */
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.reg_scp_ddr_en_mask_b = 1,
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/* [10] */
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.reg_audio_dsp_srcclkena_mask_b = 1,
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/* [11] */
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.reg_audio_dsp_infra_req_mask_b = 1,
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/* [12] */
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.reg_audio_dsp_apsrc_req_mask_b = 1,
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/* [13] */
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.reg_audio_dsp_vrf18_req_mask_b = 1,
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/* [14] */
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.reg_audio_dsp_ddr_en_mask_b = 1,
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/* [15] */
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.reg_apu_srcclkena_mask_b = 1,
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/* [16] */
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.reg_apu_infra_req_mask_b = 1,
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/* [17] */
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.reg_apu_apsrc_req_mask_b = 1,
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/* [18] */
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.reg_apu_vrf18_req_mask_b = 1,
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/* [19] */
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.reg_apu_ddr_en_mask_b = 1,
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/* [20] */
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.reg_cpueb_srcclkena_mask_b = 1,
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/* [21] */
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.reg_cpueb_infra_req_mask_b = 1,
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/* [22] */
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.reg_cpueb_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_cpueb_vrf18_req_mask_b = 1,
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/* [24] */
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.reg_cpueb_ddr_en_mask_b = 1,
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/* [25] */
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.reg_bak_psri_srcclkena_mask_b = 0,
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/* [26] */
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.reg_bak_psri_infra_req_mask_b = 0,
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/* [27] */
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.reg_bak_psri_apsrc_req_mask_b = 0,
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/* [28] */
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.reg_bak_psri_vrf18_req_mask_b = 0,
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/* [29] */
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.reg_bak_psri_ddr_en_mask_b = 0,
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/* SPM_SRC2_MASK */
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/* [0] */
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.reg_msdc0_srcclkena_mask_b = 1,
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/* [1] */
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.reg_msdc0_infra_req_mask_b = 1,
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/* [2] */
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.reg_msdc0_apsrc_req_mask_b = 1,
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/* [3] */
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.reg_msdc0_vrf18_req_mask_b = 1,
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/* [4] */
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.reg_msdc0_ddr_en_mask_b = 1,
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/* [5] */
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.reg_msdc1_srcclkena_mask_b = 1,
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/* [6] */
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.reg_msdc1_infra_req_mask_b = 1,
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/* [7] */
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.reg_msdc1_apsrc_req_mask_b = 1,
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/* [8] */
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.reg_msdc1_vrf18_req_mask_b = 1,
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/* [9] */
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.reg_msdc1_ddr_en_mask_b = 1,
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/* [10] */
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.reg_msdc2_srcclkena_mask_b = 1,
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/* [11] */
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.reg_msdc2_infra_req_mask_b = 1,
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/* [12] */
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.reg_msdc2_apsrc_req_mask_b = 1,
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/* [13] */
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.reg_msdc2_vrf18_req_mask_b = 1,
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/* [14] */
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.reg_msdc2_ddr_en_mask_b = 1,
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/* [15] */
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.reg_ufs_srcclkena_mask_b = 1,
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/* [16] */
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.reg_ufs_infra_req_mask_b = 1,
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/* [17] */
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.reg_ufs_apsrc_req_mask_b = 1,
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/* [18] */
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.reg_ufs_vrf18_req_mask_b = 1,
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/* [19] */
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.reg_ufs_ddr_en_mask_b = 1,
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/* [20] */
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.reg_usb_srcclkena_mask_b = 1,
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/* [21] */
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.reg_usb_infra_req_mask_b = 1,
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/* [22] */
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.reg_usb_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_usb_vrf18_req_mask_b = 1,
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/* [24] */
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.reg_usb_ddr_en_mask_b = 1,
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/* [25] */
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.reg_pextp_p0_srcclkena_mask_b = 1,
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/* [26] */
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.reg_pextp_p0_infra_req_mask_b = 1,
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/* [27] */
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.reg_pextp_p0_apsrc_req_mask_b = 1,
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/* [28] */
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.reg_pextp_p0_vrf18_req_mask_b = 1,
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/* [29] */
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.reg_pextp_p0_ddr_en_mask_b = 1,
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/* SPM_SRC3_MASK */
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/* [0] */
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.reg_pextp_p1_srcclkena_mask_b = 1,
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/* [1] */
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.reg_pextp_p1_infra_req_mask_b = 1,
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/* [2] */
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.reg_pextp_p1_apsrc_req_mask_b = 1,
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/* [3] */
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.reg_pextp_p1_vrf18_req_mask_b = 1,
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/* [4] */
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.reg_pextp_p1_ddr_en_mask_b = 1,
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/* [5] */
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.reg_gce0_infra_req_mask_b = 1,
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/* [6] */
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.reg_gce0_apsrc_req_mask_b = 1,
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/* [7] */
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.reg_gce0_vrf18_req_mask_b = 1,
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/* [8] */
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.reg_gce0_ddr_en_mask_b = 1,
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/* [9] */
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.reg_gce1_infra_req_mask_b = 1,
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/* [10] */
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.reg_gce1_apsrc_req_mask_b = 1,
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/* [11] */
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.reg_gce1_vrf18_req_mask_b = 1,
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/* [12] */
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.reg_gce1_ddr_en_mask_b = 1,
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/* [13] */
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.reg_spm_srcclkena_reserved_mask_b = 1,
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/* [14] */
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.reg_spm_infra_req_reserved_mask_b = 1,
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/* [15] */
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.reg_spm_apsrc_req_reserved_mask_b = 1,
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/* [16] */
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.reg_spm_vrf18_req_reserved_mask_b = 1,
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/* [17] */
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.reg_spm_ddr_en_reserved_mask_b = 1,
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/* [18] */
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.reg_disp0_apsrc_req_mask_b = 1,
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/* [19] */
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.reg_disp0_ddr_en_mask_b = 1,
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/* [20] */
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.reg_disp1_apsrc_req_mask_b = 1,
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/* [21] */
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.reg_disp1_ddr_en_mask_b = 1,
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/* [22] */
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.reg_disp2_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_disp2_ddr_en_mask_b = 1,
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/* [24] */
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.reg_disp3_apsrc_req_mask_b = 1,
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/* [25] */
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.reg_disp3_ddr_en_mask_b = 1,
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/* [26] */
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.reg_infrasys_apsrc_req_mask_b = 0,
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/* [27] */
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.reg_infrasys_ddr_en_mask_b = 1,
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/* [28] */
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.reg_cg_check_srcclkena_mask_b = 1,
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/* [29] */
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.reg_cg_check_apsrc_req_mask_b = 1,
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/* [30] */
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.reg_cg_check_vrf18_req_mask_b = 1,
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/* [31] */
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.reg_cg_check_ddr_en_mask_b = 1,
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/* SPM_SRC4_MASK */
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/* [8:0] */
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.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
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/* [17:9] */
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.reg_mcusys_merge_ddr_en_mask_b = 0x11,
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/* [19:18] */
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.reg_dramc_md32_infra_req_mask_b = 0,
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/* [21:20] */
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.reg_dramc_md32_vrf18_req_mask_b = 0,
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/* [23:22] */
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.reg_dramc_md32_ddr_en_mask_b = 0,
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/* [24] */
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.reg_dvfsrc_event_trigger_mask_b = 1,
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/* SPM_WAKEUP_EVENT_MASK2 */
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/* [3:0] */
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.reg_sc_sw2spm_wakeup_mask_b = 0,
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/* [4] */
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.reg_sc_adsp2spm_wakeup_mask_b = 0,
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/* [8:5] */
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.reg_sc_sspm2spm_wakeup_mask_b = 0,
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/* [9] */
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.reg_sc_scp2spm_wakeup_mask_b = 0,
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/* [10] */
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.reg_csyspwrup_ack_mask = 0,
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/* [11] */
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.reg_csyspwrup_req_mask = 1,
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/* SPM_WAKEUP_EVENT_MASK */
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/* [31:0] */
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.reg_wakeup_event_mask = 0xEFFFFFFF,
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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/* [31:0] */
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.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
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};
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struct spm_lp_scen __spm_vcorefs = {
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.pwrctrl = &vcorefs_ctrl,
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};
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static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
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{
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if (cmd < NR_IDX_ALL) {
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mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
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} else {
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INFO("cmd out of range!\n");
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}
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}
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void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
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{
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if (spm_dvfs_init_done == false) {
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mmio_write_32(SPM_DVFS_MISC, (mmio_read_32(SPM_DVFS_MISC) &
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~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB));
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mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
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mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
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spm_dvfs_init_done = true;
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}
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}
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void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
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const struct pwr_ctrl *src_pwr_ctrl)
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{
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uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
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SPM_FLAG_DISABLE_VCORE_DFS |
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SPM_FLAG_ENABLE_VOLTAGE_BIN;
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dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
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(src_pwr_ctrl->pcm_flags & dvfs_mask);
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if (dest_pwr_ctrl->pcm_flags_cust) {
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dest_pwr_ctrl->pcm_flags_cust = (dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
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(src_pwr_ctrl->pcm_flags & dvfs_mask);
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}
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}
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void spm_go_to_vcorefs(uint64_t spm_flags)
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{
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__spm_set_power_control(__spm_vcorefs.pwrctrl);
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__spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
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__spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
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__spm_send_cpu_wakeup_event();
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}
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uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3)
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{
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uint64_t ret = 0U;
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uint64_t cmd = x1;
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uint64_t spm_flags;
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switch (cmd) {
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case VCOREFS_SMC_CMD_0:
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spm_dvfsfw_init(x2, x3);
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break;
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case VCOREFS_SMC_CMD_1:
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spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
|
|
if (x2 & SPM_FLAG_DISABLE_VCORE_DVS)
|
|
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
|
|
if (x2 & SPM_FLAG_DISABLE_VCORE_DFS)
|
|
spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
|
|
spm_go_to_vcorefs(spm_flags);
|
|
break;
|
|
case VCOREFS_SMC_CMD_3:
|
|
spm_vcorefs_pwarp_cmd(x2, x3);
|
|
break;
|
|
case VCOREFS_SMC_CMD_2:
|
|
case VCOREFS_SMC_CMD_4:
|
|
case VCOREFS_SMC_CMD_5:
|
|
case VCOREFS_SMC_CMD_7:
|
|
default:
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void dvfsrc_init(void)
|
|
{
|
|
int i;
|
|
int count = ARRAY_SIZE(dvfsrc_init_configs);
|
|
|
|
if (dvfs_enable_done == false) {
|
|
for (i = 0; i < count; i++) {
|
|
mmio_write_32(dvfsrc_init_configs[i].offset,
|
|
dvfsrc_init_configs[i].val);
|
|
}
|
|
|
|
mmio_write_32(DVFSRC_QOS_EN, 0x0011007C);
|
|
|
|
dvfs_enable_done = true;
|
|
}
|
|
}
|
|
|
|
static void spm_vcorefs_vcore_setting(uint64_t flag)
|
|
{
|
|
spm_vcorefs_pwarp_cmd(3, __vcore_uv_to_pmic(vcore_opp_3_uv));
|
|
spm_vcorefs_pwarp_cmd(2, __vcore_uv_to_pmic(vcore_opp_2_uv));
|
|
spm_vcorefs_pwarp_cmd(1, __vcore_uv_to_pmic(vcore_opp_1_uv));
|
|
spm_vcorefs_pwarp_cmd(0, __vcore_uv_to_pmic(vcore_opp_0_uv));
|
|
}
|
|
|
|
int spm_vcorefs_get_vcore(unsigned int gear)
|
|
{
|
|
int ret_val;
|
|
|
|
switch (gear) {
|
|
case 3:
|
|
ret_val = vcore_opp_0_uv;
|
|
break;
|
|
case 2:
|
|
ret_val = vcore_opp_1_uv;
|
|
break;
|
|
case 1:
|
|
ret_val = vcore_opp_2_uv;
|
|
break;
|
|
case 0:
|
|
default:
|
|
ret_val = vcore_opp_3_uv;
|
|
break;
|
|
}
|
|
return ret_val;
|
|
}
|
|
|
|
uint64_t spm_vcorefs_v2_args(u_register_t x1, u_register_t x2, u_register_t x3, u_register_t *x4)
|
|
{
|
|
uint64_t ret = 0U;
|
|
uint64_t cmd = x1;
|
|
uint64_t spm_flags;
|
|
|
|
switch (cmd) {
|
|
case VCOREFS_SMC_CMD_INIT:
|
|
/* vcore_dvfs init + kick */
|
|
spm_dvfsfw_init(0, 0);
|
|
spm_vcorefs_vcore_setting(x3 & 0xF);
|
|
spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
|
|
if (x2 & 0x1) {
|
|
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
|
|
}
|
|
if (x2 & 0x2) {
|
|
spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
|
|
}
|
|
spm_go_to_vcorefs(spm_flags);
|
|
dvfsrc_init();
|
|
*x4 = 0U;
|
|
break;
|
|
case VCOREFS_SMC_CMD_OPP_TYPE:
|
|
/* get dram type */
|
|
*x4 = 0U;
|
|
break;
|
|
case VCOREFS_SMC_CMD_FW_TYPE:
|
|
*x4 = 0U;
|
|
break;
|
|
case VCOREFS_SMC_CMD_GET_UV:
|
|
*x4 = spm_vcorefs_get_vcore(x2);
|
|
break;
|
|
case VCOREFS_SMC_CMD_GET_NUM_V:
|
|
*x4 = VCORE_MAX_OPP;
|
|
break;
|
|
case VCOREFS_SMC_CMD_GET_NUM_F:
|
|
*x4 = DRAM_MAX_OPP;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|