136 lines
6.0 KiB
C
136 lines
6.0 KiB
C
/*
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* Copyright(C)2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_SPM_VCOREFS_H
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#define MT_SPM_VCOREFS_H
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uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4);
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enum vcorefs_smc_cmd {
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VCOREFS_SMC_CMD_0,
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VCOREFS_SMC_CMD_1,
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VCOREFS_SMC_CMD_2,
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VCOREFS_SMC_CMD_3,
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VCOREFS_SMC_CMD_4,
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/* check spmfw status */
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VCOREFS_SMC_CMD_5,
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/* get spmfw type */
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VCOREFS_SMC_CMD_6,
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/* get spm reg status */
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VCOREFS_SMC_CMD_7,
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NUM_VCOREFS_SMC_CMD,
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};
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enum vcorefs_smc_cmd_new {
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VCOREFS_SMC_CMD_INIT = 0,
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VCOREFS_SMC_CMD_KICK = 1,
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};
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#define _VCORE_BASE_UV 400000
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#define _VCORE_STEP_UV 6250
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/* PMIC */
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#define __vcore_pmic_to_uv(pmic) \
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(((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV)
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#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \
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((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV)
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struct reg_config {
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uint32_t offset;
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uint32_t val;
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};
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#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
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#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
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#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
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#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
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#define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0)
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#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
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#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
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#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
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#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
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#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
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#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C)
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#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110)
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#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114)
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#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118)
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#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C)
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#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280)
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#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294)
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#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610)
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#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614)
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#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00)
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#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04)
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#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08)
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#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C)
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#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10)
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#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14)
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#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18)
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#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34)
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#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38)
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#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C)
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#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40)
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#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44)
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#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60)
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#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4)
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#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8)
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#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC)
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#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0)
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#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4)
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#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8)
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#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC)
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#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0)
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#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4)
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#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8)
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#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC)
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#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0)
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#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4)
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#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8)
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#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC)
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#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00)
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#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04)
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#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08)
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#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C)
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#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0)
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#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4)
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#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8)
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#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC)
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#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00)
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#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04)
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#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08)
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#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C)
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#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0)
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#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4)
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#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8)
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#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC)
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#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00)
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#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04)
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#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08)
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#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C)
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#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10)
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#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14)
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#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18)
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#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C)
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#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38)
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#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C)
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#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C)
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#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50)
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#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54)
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#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58)
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#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C)
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#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60)
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#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64)
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#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68)
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#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C)
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#define VCORE_VB_EFUSE (0x11C105E8)
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#endif /* MT_SPM_VCOREFS_H */
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