94 lines
2.9 KiB
ArmAsm
94 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <el2_common_macros.S>
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#include <lib/xlat_mpu/xlat_mpu.h>
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.globl bl1_entrypoint
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.globl bl1_run_next_image
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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func bl1_entrypoint
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/* ---------------------------------------------------------------------
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* If the reset address is programmable then bl1_entrypoint() is
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* executed only on the cold boot path. Therefore, we can skip the warm
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* boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el2_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl1_exceptions \
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_pie_fixup_size=0
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/* --------------------------------------------------------------------
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* Perform BL1 setup
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* --------------------------------------------------------------------
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*/
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bl bl1_setup
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/* --------------------------------------------------------------------
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* Initialize platform and jump to our c-entry point
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* for this type of reset.
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* --------------------------------------------------------------------
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*/
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bl bl1_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl1_entrypoint
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func bl1_run_next_image
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mov x20,x0
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/* ---------------------------------------------
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* MPU needs to be disabled because both BL1 and BL33 execute
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* in EL2, and therefore share the same address space.
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* BL33 will initialize the address space according to its
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* own requirement.
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* ---------------------------------------------
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*/
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bl disable_mpu_icache_el2
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/* ---------------------------------------------
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* Wipe clean and disable all MPU regions. This function expects
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* that the MPU has already been turned off, and caching concerns
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* addressed, but it also explicitly turns off the MPU.
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* ---------------------------------------------
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*/
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bl clear_all_mpu_regions
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/* --------------------------------------------------
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* Do the transition to next boot image.
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* --------------------------------------------------
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*/
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el2, x0
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msr spsr_el2, x1
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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exception_return
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endfunc bl1_run_next_image
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