406 lines
11 KiB
C
406 lines
11 KiB
C
/*
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* Copyright(C)2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <stdio.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <lib/utils_def.h>
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#include <mtk_sip_svc.h>
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#include <plat_pm.h>
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#include <platform_def.h>
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#include "mt_spm.h"
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#include "mt_spm_internal.h"
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#include "mt_spm_reg.h"
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#include "mt_spm_vcorefs.h"
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#include "mt_spm_pmic_wrap.h"
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#define VCORE_CT_ENABLE (1U << 5)
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#define SW_REQ5_INIT_VAL (6U << 12)
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#define V_VMODE_SHIFT 0
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#define VCORE_HV 105
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#define VCORE_LV 95
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#define PMIC_STEP_UV 6250
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static const struct reg_config dvfsrc_init_configs[] = {
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/* Setup opp table */
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{ DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
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{ DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
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{ DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
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{ DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
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{ DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
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{ DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
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{ DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
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{ DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
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{ DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
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{ DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
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{ DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
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/* Setup hw emi qos policy */
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{ DVFSRC_DDR_REQUEST, 0x00004321 },
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{ DVFSRC_DDR_REQUEST3, 0x00000065 },
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/* Setup up for PCIe */
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{ DVFSRC_PCIE_VCORE_REQ, 0x0A298001 },
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/* Setup up HRT QOS policy */
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{ DVFSRC_HRT_BW_BASE, 0x00000004 },
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{ DVFSRC_HRT_REQ_UNIT, 0x0000001E },
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{ DVFSRC_HRT_HIGH_3, 0x18A618A6 },
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{ DVFSRC_HRT_HIGH_2, 0x18A61183 },
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{ DVFSRC_HRT_HIGH_1, 0x0D690B80 },
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{ DVFSRC_HRT_HIGH, 0x070804B0 },
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{ DVFSRC_HRT_LOW_3, 0x18A518A5 },
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{ DVFSRC_HRT_LOW_2, 0x18A51182 },
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{ DVFSRC_HRT_LOW_1, 0x0D680B7F },
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{ DVFSRC_HRT_LOW, 0x070704AF },
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{ DVFSRC_HRT_REQUEST, 0x66654321 },
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/* Setup up SRT QOS policy */
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{ DVFSRC_QOS_EN, 0x0011007C },
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{ DVFSRC_DDR_QOS0, 0x00000019 },
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{ DVFSRC_DDR_QOS1, 0x00000026 },
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{ DVFSRC_DDR_QOS2, 0x00000033 },
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{ DVFSRC_DDR_QOS3, 0x0000003B },
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{ DVFSRC_DDR_QOS4, 0x0000004C },
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{ DVFSRC_DDR_QOS5, 0x00000066 },
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{ DVFSRC_DDR_QOS6, 0x00000066 },
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{ DVFSRC_DDR_REQUEST5, 0x54321000 },
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{ DVFSRC_DDR_REQUEST7, 0x66000000 },
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/* Setup up hifi request policy */
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{ DVFSRC_DDR_REQUEST6, 0x66543210 },
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/* Setup up hw request vcore policy */
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{ DVFSRC_VCORE_USER_REQ, 0x00010A29 },
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/* Setup misc*/
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{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
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{ DVFSRC_RSRV_5, 0x00000001 },
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{ DVFSRC_INT_EN, 0x00000002 },
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/* Init opp and enable dvfsrc*/
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{ DVFSRC_CURRENT_FORCE, 0x00000001 },
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{ DVFSRC_BASIC_CONTROL, 0x0298444B },
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{ DVFSRC_BASIC_CONTROL, 0x0298054B },
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{ DVFSRC_CURRENT_FORCE, 0x00000000 },
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};
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static struct pwr_ctrl vcorefs_ctrl = {
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.wake_src = R12_REG_CPU_WAKEUP,
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/* default VCORE DVFS is disabled */
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.pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
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SPM_FLAG_DISABLE_VCORE_DVS |
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SPM_FLAG_DISABLE_VCORE_DFS),
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/* Auto-gen Start */
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/* SPM_AP_STANDBY_CON */
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.reg_wfi_op = 0,
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.reg_wfi_type = 0,
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.reg_mp0_cputop_idle_mask = 0,
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.reg_mp1_cputop_idle_mask = 0,
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.reg_mcusys_idle_mask = 0,
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.reg_md_apsrc_1_sel = 0,
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.reg_md_apsrc_0_sel = 0,
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.reg_conn_apsrc_sel = 0,
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/* SPM_SRC_REQ */
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.reg_spm_apsrc_req = 0,
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.reg_spm_f26m_req = 0,
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.reg_spm_infra_req = 0,
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.reg_spm_vrf18_req = 0,
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.reg_spm_ddr_en_req = 1,
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.reg_spm_dvfs_req = 0,
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.reg_spm_sw_mailbox_req = 0,
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.reg_spm_sspm_mailbox_req = 0,
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.reg_spm_adsp_mailbox_req = 0,
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.reg_spm_scp_mailbox_req = 0,
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/* SPM_SRC6_MASK */
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.reg_dpmaif_srcclkena_mask_b = 1,
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.reg_dpmaif_infra_req_mask_b = 1,
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.reg_dpmaif_apsrc_req_mask_b = 1,
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.reg_dpmaif_vrf18_req_mask_b = 1,
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.reg_dpmaif_ddr_en_mask_b = 1,
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/* SPM_SRC_MASK */
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.reg_md_srcclkena_0_mask_b = 1,
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.reg_md_srcclkena2infra_req_0_mask_b = 0,
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.reg_md_apsrc2infra_req_0_mask_b = 1,
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.reg_md_apsrc_req_0_mask_b = 1,
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.reg_md_vrf18_req_0_mask_b = 1,
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.reg_md_ddr_en_0_mask_b = 1,
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.reg_md_srcclkena_1_mask_b = 0,
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.reg_md_srcclkena2infra_req_1_mask_b = 0,
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.reg_md_apsrc2infra_req_1_mask_b = 0,
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.reg_md_apsrc_req_1_mask_b = 0,
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.reg_md_vrf18_req_1_mask_b = 0,
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.reg_md_ddr_en_1_mask_b = 0,
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.reg_conn_srcclkena_mask_b = 1,
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.reg_conn_srcclkenb_mask_b = 0,
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.reg_conn_infra_req_mask_b = 1,
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.reg_conn_apsrc_req_mask_b = 1,
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.reg_conn_vrf18_req_mask_b = 1,
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.reg_conn_ddr_en_mask_b = 1,
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.reg_conn_vfe28_mask_b = 0,
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.reg_srcclkeni0_srcclkena_mask_b = 1,
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.reg_srcclkeni0_infra_req_mask_b = 1,
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.reg_srcclkeni1_srcclkena_mask_b = 0,
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.reg_srcclkeni1_infra_req_mask_b = 0,
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.reg_srcclkeni2_srcclkena_mask_b = 0,
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.reg_srcclkeni2_infra_req_mask_b = 0,
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.reg_infrasys_apsrc_req_mask_b = 0,
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.reg_infrasys_ddr_en_mask_b = 1,
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.reg_md32_srcclkena_mask_b = 1,
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.reg_md32_infra_req_mask_b = 1,
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.reg_md32_apsrc_req_mask_b = 1,
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.reg_md32_vrf18_req_mask_b = 1,
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.reg_md32_ddr_en_mask_b = 1,
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/* SPM_SRC2_MASK */
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.reg_scp_srcclkena_mask_b = 1,
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.reg_scp_infra_req_mask_b = 1,
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.reg_scp_apsrc_req_mask_b = 1,
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.reg_scp_vrf18_req_mask_b = 1,
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.reg_scp_ddr_en_mask_b = 1,
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.reg_audio_dsp_srcclkena_mask_b = 1,
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.reg_audio_dsp_infra_req_mask_b = 1,
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.reg_audio_dsp_apsrc_req_mask_b = 1,
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.reg_audio_dsp_vrf18_req_mask_b = 1,
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.reg_audio_dsp_ddr_en_mask_b = 1,
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.reg_ufs_srcclkena_mask_b = 1,
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.reg_ufs_infra_req_mask_b = 1,
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.reg_ufs_apsrc_req_mask_b = 1,
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.reg_ufs_vrf18_req_mask_b = 1,
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.reg_ufs_ddr_en_mask_b = 1,
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.reg_disp0_apsrc_req_mask_b = 1,
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.reg_disp0_ddr_en_mask_b = 1,
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.reg_disp1_apsrc_req_mask_b = 1,
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.reg_disp1_ddr_en_mask_b = 1,
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.reg_gce_infra_req_mask_b = 1,
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.reg_gce_apsrc_req_mask_b = 1,
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.reg_gce_vrf18_req_mask_b = 1,
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.reg_gce_ddr_en_mask_b = 1,
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.reg_apu_srcclkena_mask_b = 1,
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.reg_apu_infra_req_mask_b = 1,
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.reg_apu_apsrc_req_mask_b = 1,
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.reg_apu_vrf18_req_mask_b = 1,
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.reg_apu_ddr_en_mask_b = 1,
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.reg_cg_check_srcclkena_mask_b = 0,
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.reg_cg_check_apsrc_req_mask_b = 0,
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.reg_cg_check_vrf18_req_mask_b = 0,
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.reg_cg_check_ddr_en_mask_b = 0,
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/* SPM_SRC3_MASK */
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.reg_dvfsrc_event_trigger_mask_b = 1,
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.reg_sw2spm_int0_mask_b = 0,
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.reg_sw2spm_int1_mask_b = 0,
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.reg_sw2spm_int2_mask_b = 0,
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.reg_sw2spm_int3_mask_b = 0,
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.reg_sc_adsp2spm_wakeup_mask_b = 0,
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.reg_sc_sspm2spm_wakeup_mask_b = 0,
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.reg_sc_scp2spm_wakeup_mask_b = 0,
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.reg_csyspwrreq_mask = 1,
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.reg_spm_srcclkena_reserved_mask_b = 0,
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.reg_spm_infra_req_reserved_mask_b = 0,
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.reg_spm_apsrc_req_reserved_mask_b = 0,
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.reg_spm_vrf18_req_reserved_mask_b = 0,
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.reg_spm_ddr_en_reserved_mask_b = 0,
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.reg_mcupm_srcclkena_mask_b = 1,
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.reg_mcupm_infra_req_mask_b = 1,
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.reg_mcupm_apsrc_req_mask_b = 1,
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.reg_mcupm_vrf18_req_mask_b = 1,
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.reg_mcupm_ddr_en_mask_b = 1,
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.reg_msdc0_srcclkena_mask_b = 1,
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.reg_msdc0_infra_req_mask_b = 1,
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.reg_msdc0_apsrc_req_mask_b = 1,
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.reg_msdc0_vrf18_req_mask_b = 1,
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.reg_msdc0_ddr_en_mask_b = 1,
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.reg_msdc1_srcclkena_mask_b = 1,
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.reg_msdc1_infra_req_mask_b = 1,
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.reg_msdc1_apsrc_req_mask_b = 1,
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.reg_msdc1_vrf18_req_mask_b = 1,
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.reg_msdc1_ddr_en_mask_b = 1,
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/* SPM_SRC4_MASK */
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.ccif_event_mask_b = 0xFFF,
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.reg_bak_psri_srcclkena_mask_b = 0,
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.reg_bak_psri_infra_req_mask_b = 0,
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.reg_bak_psri_apsrc_req_mask_b = 0,
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.reg_bak_psri_vrf18_req_mask_b = 0,
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.reg_bak_psri_ddr_en_mask_b = 0,
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.reg_dramc0_md32_infra_req_mask_b = 1,
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.reg_dramc0_md32_vrf18_req_mask_b = 0,
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.reg_dramc1_md32_infra_req_mask_b = 1,
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.reg_dramc1_md32_vrf18_req_mask_b = 0,
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.reg_conn_srcclkenb2pwrap_mask_b = 0,
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.reg_dramc0_md32_wakeup_mask = 1,
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.reg_dramc1_md32_wakeup_mask = 1,
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/* SPM_SRC5_MASK */
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.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
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.reg_mcusys_merge_ddr_en_mask_b = 0x11,
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.reg_msdc2_srcclkena_mask_b = 1,
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.reg_msdc2_infra_req_mask_b = 1,
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.reg_msdc2_apsrc_req_mask_b = 1,
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.reg_msdc2_vrf18_req_mask_b = 1,
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.reg_msdc2_ddr_en_mask_b = 1,
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.reg_pcie_srcclkena_mask_b = 1,
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.reg_pcie_infra_req_mask_b = 1,
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.reg_pcie_apsrc_req_mask_b = 1,
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.reg_pcie_vrf18_req_mask_b = 1,
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.reg_pcie_ddr_en_mask_b = 1,
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/* SPM_WAKEUP_EVENT_MASK */
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.reg_wakeup_event_mask = 0xEFFFFFFF,
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
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/* Auto-gen End */
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};
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struct spm_lp_scen __spm_vcorefs = {
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.pwrctrl = &vcorefs_ctrl,
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};
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static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
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{
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if (cmd < NR_IDX_ALL) {
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mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
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} else {
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INFO("cmd out of range!\n");
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}
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}
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void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
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{
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mmio_clrsetbits_32(SPM_DVFS_MISC, SPM_DVFS_FORCE_ENABLE_LSB,
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SPM_DVFSRC_ENABLE_LSB);
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mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
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mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
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}
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void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
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const struct pwr_ctrl *src_pwr_ctrl)
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{
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uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
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SPM_FLAG_DISABLE_VCORE_DFS |
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SPM_FLAG_ENABLE_VOLTAGE_BIN;
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dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
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(src_pwr_ctrl->pcm_flags & dvfs_mask);
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if (dest_pwr_ctrl->pcm_flags_cust > 0U) {
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dest_pwr_ctrl->pcm_flags_cust =
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(dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
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(src_pwr_ctrl->pcm_flags & dvfs_mask);
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}
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}
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static void spm_go_to_vcorefs(void)
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{
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__spm_set_power_control(__spm_vcorefs.pwrctrl);
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__spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
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__spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
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__spm_send_cpu_wakeup_event();
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}
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static void dvfsrc_init(void)
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{
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) {
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mmio_write_32(dvfsrc_init_configs[i].offset,
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dvfsrc_init_configs[i].val);
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}
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}
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static uint32_t spm_vcorefs_get_efuse_data(void)
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{
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return mmio_read_32(VCORE_VB_EFUSE);
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}
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static uint32_t is_rising_need(void)
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{
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return ((spm_vcorefs_get_efuse_data() & 0xF) == 11U) ? 1U : 0U;
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}
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static void spm_vcorefs_vcore_setting(uint64_t flag)
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{
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uint32_t dvfs_v_mode, dvfsrc_rsrv, i;
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uint32_t opp_uv[] = {725000U, 650000U, 600000U, 575000U};
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dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4);
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dvfs_v_mode = (dvfsrc_rsrv >> V_VMODE_SHIFT) & 0x3;
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if (is_rising_need() != 0U) {
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opp_uv[2] = 625000U;
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opp_uv[3] = 600000U;
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}
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for (i = 0; i < ARRAY_SIZE(opp_uv); i++) {
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if (dvfs_v_mode == 3U) {
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/* LV */
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opp_uv[i] = round_down((opp_uv[i] * VCORE_LV) / 100U,
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PMIC_STEP_UV);
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} else if (dvfs_v_mode == 1U) {
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/* HV */
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opp_uv[i] = round_up((opp_uv[i] * VCORE_HV) / 100U,
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PMIC_STEP_UV);
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}
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spm_vcorefs_pwarp_cmd(i, __vcore_uv_to_pmic(opp_uv[i]));
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}
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}
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uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4)
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{
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uint64_t cmd = x1;
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uint64_t spm_flags;
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switch (cmd) {
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case VCOREFS_SMC_CMD_INIT:
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/* vcore_dvfs init + kick */
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mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL);
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spm_dvfsfw_init(0ULL, 0ULL);
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spm_vcorefs_vcore_setting(x3 & 0xF);
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spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
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if ((x2 & 0x1) > 0U) {
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spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
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}
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if ((x2 & 0x2) > 0U) {
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spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
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}
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if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) {
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spm_flags |= SPM_FLAG_ENABLE_VOLTAGE_BIN;
|
|
}
|
|
|
|
set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags);
|
|
spm_go_to_vcorefs();
|
|
dvfsrc_init();
|
|
|
|
*x4 = 0U;
|
|
mmio_write_32(DVFSRC_SW_REQ5, 0U);
|
|
break;
|
|
case VCOREFS_SMC_CMD_KICK:
|
|
mmio_write_32(DVFSRC_SW_REQ5, 0U);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0ULL;
|
|
}
|