236 lines
6.9 KiB
C
236 lines
6.9 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mt_spm_cond.h>
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#include <mt_spm_conservation.h>
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#include <mt_spm_constraint.h>
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#include <plat_mtk_lpm.h>
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#include <plat_pm.h>
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#include <platform_def.h>
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#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
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#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
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#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEN_BASE + ofs)
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#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
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#define MT_LP_TZ_VPPSYS0_REG(ofs) (VPPSYS0_BASE + ofs)
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#define MT_LP_TZ_VPPSYS1_REG(ofs) (VPPSYS1_BASE + ofs)
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#define MT_LP_TZ_VDOSYS0_REG(ofs) (VDOSYS0_BASE + ofs)
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#define MT_LP_TZ_VDOSYS1_REG(ofs) (VDOSYS1_BASE + ofs)
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#define MT_LP_TZ_PERI_AO_REG(ofs) (PERICFG_AO_BASE + ofs)
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#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C)
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#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170)
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#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0094)
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#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0090)
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#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC)
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#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8)
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#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00E8)
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#define TOP_SW_I2C_CG MT_LP_TZ_TOPCK_REG(0x00BC)
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#define PERI_SW_CG0 MT_LP_TZ_PERI_AO_REG(0x0018)
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#define VPPSYS0_SW_CG0 MT_LP_TZ_VPPSYS0_REG(0x0020)
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#define VPPSYS0_SW_CG1 MT_LP_TZ_VPPSYS0_REG(0x002C)
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#define VPPSYS0_SW_CG2 MT_LP_TZ_VPPSYS0_REG(0x0038)
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#define VPPSYS1_SW_CG0 MT_LP_TZ_VPPSYS1_REG(0x0100)
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#define VPPSYS1_SW_CG1 MT_LP_TZ_VPPSYS1_REG(0x0110)
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#define VDOSYS0_SW_CG0 MT_LP_TZ_VDOSYS0_REG(0x0100)
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#define VDOSYS0_SW_CG1 MT_LP_TZ_VDOSYS0_REG(0x0110)
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#define VDOSYS1_SW_CG0 MT_LP_TZ_VDOSYS1_REG(0x0100)
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#define VDOSYS1_SW_CG1 MT_LP_TZ_VDOSYS1_REG(0x0120)
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#define VDOSYS1_SW_CG2 MT_LP_TZ_VDOSYS1_REG(0x0130)
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/***********************************************************
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* Check clkmux registers
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***********************************************************/
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#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x98 + id * 0x10)
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#define PDN_CHECK BIT(7)
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#define CLK_CHECK BIT(31)
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enum {
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CLKMUX_DISP = 0,
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NF_CLKMUX,
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};
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static bool is_clkmux_pdn(unsigned int clkmux_id)
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{
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unsigned int reg, val, idx;
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if ((clkmux_id & CLK_CHECK) != 0U) {
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clkmux_id = (clkmux_id & ~CLK_CHECK);
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reg = clkmux_id / 4U;
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val = mmio_read_32(CLK_CFG(reg));
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idx = clkmux_id % 4U;
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val = (val >> (idx * 8U)) & PDN_CHECK;
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return (val != 0U);
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}
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return false;
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}
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static struct mt_spm_cond_tables spm_cond_t;
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struct idle_cond_info {
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unsigned int subsys_mask;
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uintptr_t addr;
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bool bBitflip;
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unsigned int clkmux_id;
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};
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#define IDLE_CG(mask, addr, bitflip, clkmux) \
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{mask, (uintptr_t)addr, bitflip, clkmux}
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static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
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IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
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IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0U),
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IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0U),
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IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0U),
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IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0U),
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IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0U),
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IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0U),
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IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00000800, VPPSYS0_SW_CG2, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00001000, VPPSYS1_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00001000, VPPSYS1_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00002000, VDOSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00002000, VDOSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00004000, VDOSYS1_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00004000, VDOSYS1_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00004000, VDOSYS1_SW_CG2, true, (CLK_CHECK|CLKMUX_DISP)),
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IDLE_CG(0x00000080, TOP_SW_I2C_CG, true, (CLK_CHECK|CLKMUX_DISP)),
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};
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/***********************************************************
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* Check pll idle condition
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***********************************************************/
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#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x340)
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#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x0E0)
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#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x1F0)
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#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x710)
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#define PLL_TVDPLL MT_LP_TZ_APMIXEDSYS(0x380)
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unsigned int mt_spm_cond_check(int state_id,
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const struct mt_spm_cond_tables *src,
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const struct mt_spm_cond_tables *dest,
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struct mt_spm_cond_tables *res)
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{
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unsigned int blocked = 0U, i;
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bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
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if ((src == NULL) || (dest == NULL)) {
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return SPM_COND_CHECK_FAIL;
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}
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for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
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if (res != NULL) {
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res->table_cg[i] =
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(src->table_cg[i] & dest->table_cg[i]);
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if (is_system_suspend && (res->table_cg[i] != 0U)) {
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INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
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dest->name, i, idle_cg_info[i].addr,
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res->table_cg[i]);
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}
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if (res->table_cg[i] != 0U) {
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blocked |= (1U << i);
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}
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} else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
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blocked |= (1U << i);
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break;
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}
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}
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if (res != NULL) {
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res->table_pll = (src->table_pll & dest->table_pll);
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if (res->table_pll != 0U) {
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blocked |=
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(res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
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SPM_COND_CHECK_BLOCKED_PLL;
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}
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} else if ((src->table_pll & dest->table_pll) != 0U) {
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blocked |= SPM_COND_CHECK_BLOCKED_PLL;
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}
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if (is_system_suspend && (blocked != 0U)) {
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INFO("suspend: %s blocked=0x%08x\n", dest->name, blocked);
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}
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return blocked;
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}
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#define IS_MT_SPM_PWR_OFF(mask) \
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(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
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((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
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int mt_spm_cond_update(struct mt_resource_constraint **con,
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int stateid, void *priv)
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{
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int res;
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uint32_t i;
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struct mt_resource_constraint *const *rc;
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/* read all cg state */
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for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
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spm_cond_t.table_cg[i] = 0U;
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/* check mtcmos, if off set idle_value and clk to 0 disable */
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if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
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continue;
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}
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/* check clkmux */
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if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
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continue;
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}
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spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
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~mmio_read_32(idle_cg_info[i].addr) :
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mmio_read_32(idle_cg_info[i].addr);
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}
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spm_cond_t.table_pll = 0U;
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if ((mmio_read_32(PLL_MFGPLL) & 0x200) != 0U) {
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spm_cond_t.table_pll |= PLL_BIT_MFGPLL;
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}
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if ((mmio_read_32(PLL_MMPLL) & 0x200) != 0U) {
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spm_cond_t.table_pll |= PLL_BIT_MMPLL;
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}
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if ((mmio_read_32(PLL_UNIVPLL) & 0x200) != 0U) {
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spm_cond_t.table_pll |= PLL_BIT_UNIVPLL;
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}
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if ((mmio_read_32(PLL_MSDCPLL) & 0x200) != 0U) {
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spm_cond_t.table_pll |= PLL_BIT_MSDCPLL;
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}
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if ((mmio_read_32(PLL_TVDPLL) & 0x200) != 0U) {
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spm_cond_t.table_pll |= PLL_BIT_TVDPLL;
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}
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spm_cond_t.priv = priv;
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for (rc = con; *rc != NULL; rc++) {
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if (((*rc)->update) == NULL) {
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continue;
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}
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res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION,
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(void const *)&spm_cond_t);
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if (res != MT_RM_STATUS_OK) {
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break;
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}
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}
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return 0;
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}
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