160 lines
4.2 KiB
C
160 lines
4.2 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mt_spm.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_pmic_wrap.h>
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#include <mt_spm_reg.h>
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#include <plat_pm.h>
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#include <platform_def.h>
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/* PMIC_WRAP MT6359 */
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#define VCORE_BASE_UV 40000
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#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
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#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
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#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
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#define SPM_DATA_SHIFT 16
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#define BUCK_VGPU11_ELR0 0x15B4
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#define TOP_SPI_CON0 0x0456
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#define BUCK_TOP_CON1 0x1443
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#define TOP_CON 0x0013
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#define TOP_DIG_WPK 0x03a9
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#define TOP_CON_LOCK 0x03a8
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#define TOP_CLK_CON0 0x0134
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struct pmic_wrap_cmd {
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unsigned long cmd_addr;
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unsigned long cmd_wdata;
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};
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struct pmic_wrap_setting {
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enum pmic_wrap_phase_id phase;
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struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
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struct {
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struct {
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unsigned long cmd_addr;
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unsigned long cmd_wdata;
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} _[NR_PMIC_WRAP_CMD];
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const int nr_idx;
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} set[NR_PMIC_WRAP_PHASE];
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};
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static struct pmic_wrap_setting pw = {
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.phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
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.addr = { {0UL, 0UL} },
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.set[PMIC_WRAP_PHASE_ALLINONE] = {
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._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(75000),},
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._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
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._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
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._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(55000),},
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._[CMD_4] = {TOP_SPI_CON0, 0x1,},
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._[CMD_5] = {TOP_SPI_CON0, 0x0,},
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._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
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._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
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._[CMD_8] = {TOP_CON, 0x3,},
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._[CMD_9] = {TOP_CON, 0x0,},
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._[CMD_10] = {TOP_DIG_WPK, 0x63,},
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._[CMD_11] = {TOP_CON_LOCK, 0x15,},
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._[CMD_12] = {TOP_DIG_WPK, 0x0,},
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._[CMD_13] = {TOP_CON_LOCK, 0x0,},
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._[CMD_14] = {TOP_CLK_CON0, 0x40,},
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._[CMD_15] = {TOP_CLK_CON0, 0x0,},
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.nr_idx = NR_IDX_ALL,
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},
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};
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void _mt_spm_pmic_table_init(void)
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{
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struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
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{(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
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{(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
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{(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
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{(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
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{(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
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{(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
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{(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
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{(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
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{(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
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{(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
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{(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
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{(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
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{(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
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{(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
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{(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
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{(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
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};
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memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
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}
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void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
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{
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uint32_t idx, addr, data;
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if (phase >= NR_PMIC_WRAP_PHASE) {
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return;
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}
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if (pw.phase == phase) {
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return;
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}
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if (pw.addr[0].cmd_addr == 0UL) {
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_mt_spm_pmic_table_init();
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}
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pw.phase = phase;
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mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
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for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
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addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
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data = pw.set[phase]._[idx].cmd_wdata;
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mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
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}
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}
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void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
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uint32_t cmd_wdata)
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{
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uint32_t addr;
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if (phase >= NR_PMIC_WRAP_PHASE) {
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return;
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}
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if (idx >= pw.set[phase].nr_idx) {
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return;
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}
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pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
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mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
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if (pw.phase == phase) {
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addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
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mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
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}
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}
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uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
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{
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if (phase >= NR_PMIC_WRAP_PHASE) {
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return 0UL;
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}
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if (idx >= pw.set[phase].nr_idx) {
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return 0UL;
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}
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return pw.set[phase]._[idx].cmd_wdata;
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}
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