224 lines
5.1 KiB
C
224 lines
5.1 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <string.h>
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#include <common/debug.h>
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#include <dcfg.h>
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#include <drivers/delay_timer.h>
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#include <fuse_prov.h>
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#include <io_block.h>
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#include <io_driver.h>
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#include <io_fip.h>
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#include <io_memmap.h>
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#include <io_storage.h>
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#include <lib/utils.h>
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#include <nxp_gpio.h>
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#include <sfp.h>
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#include <sfp_error_codes.h>
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#include <tools_share/firmware_image_package.h>
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#include "fuse_io.h"
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#include <load_img.h>
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#include <plat/common/platform.h>
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#include "plat_common.h"
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#include "platform_def.h"
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extern uintptr_t backend_dev_handle;
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static uint32_t fuse_fip;
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static uintptr_t fuse_fip_dev_handle;
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static io_block_spec_t fuse_fip_block_spec = {
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.offset = PLAT_FUSE_FIP_OFFSET,
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.length = PLAT_FUSE_FIP_MAX_SIZE
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};
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static const io_uuid_spec_t fuse_prov_uuid_spec = {
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.uuid = UUID_FUSE_PROV,
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};
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static const io_uuid_spec_t fuse_up_uuid_spec = {
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.uuid = UUID_FUSE_UP,
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};
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static int open_fuse_fip(const uintptr_t spec);
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struct plat_io_policy {
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uintptr_t *dev_handle;
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uintptr_t image_spec;
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int (*check)(const uintptr_t spec);
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};
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/* By default, ARM platforms load images from the FIP */
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static const struct plat_io_policy fuse_policies[] = {
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[FUSE_FIP_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
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&backend_dev_handle,
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(uintptr_t)&fuse_fip_block_spec,
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NULL
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},
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[FUSE_PROV_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
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&fuse_fip_dev_handle,
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(uintptr_t)&fuse_prov_uuid_spec,
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open_fuse_fip
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},
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[FUSE_UP_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
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&fuse_fip_dev_handle,
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(uintptr_t)&fuse_up_uuid_spec,
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open_fuse_fip
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}
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};
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static int open_fuse_fip(const uintptr_t spec)
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{
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int result;
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uintptr_t local_image_handle;
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/* See if a Firmware Image Package is available */
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result = io_dev_init(fuse_fip_dev_handle, (uintptr_t)FUSE_FIP_IMAGE_ID);
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if (result == 0) {
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result = io_open(fuse_fip_dev_handle,
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spec,
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&local_image_handle);
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if (result == 0) {
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VERBOSE("Using FIP\n");
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io_close(local_image_handle);
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}
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}
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return result;
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}
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/* The image can be one of the DDR PHY images, which can be sleected via DDR
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* policies
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*/
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int plat_get_fuse_image_source(unsigned int image_id,
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uintptr_t *dev_handle,
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uintptr_t *image_spec,
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int (*check)(const uintptr_t spec))
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{
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int result;
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const struct plat_io_policy *policy;
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assert(image_id < (FUSE_FIP_IMAGE_ID + ARRAY_SIZE(fuse_policies)));
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policy = &fuse_policies[image_id - FUSE_FIP_IMAGE_ID];
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if (image_id == FUSE_FIP_IMAGE_ID) {
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result = check(policy->image_spec);
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} else {
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result = policy->check(policy->image_spec);
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}
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if (result == 0) {
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*image_spec = policy->image_spec;
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*dev_handle = *(policy->dev_handle);
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}
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return result;
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}
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int fuse_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev)
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{
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int io_result;
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size_t fuse_fip_offset = PLAT_FUSE_FIP_OFFSET;
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/* Open connections to fuse fip and cache the handles */
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io_result = io_dev_open(fip_dev_con, (uintptr_t)&fuse_fip,
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&fuse_fip_dev_handle);
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assert(io_result == 0);
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switch (boot_dev) {
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#if QSPI_BOOT
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case BOOT_DEVICE_QSPI:
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fuse_fip_offset += NXP_QSPI_FLASH_ADDR;
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break;
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#endif
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#if NOR_BOOT
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case BOOT_DEVICE_IFC_NOR:
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fuse_fip_offset += NXP_NOR_FLASH_ADDR;
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break;
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#endif
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#if FLEXSPI_NOR_BOOT
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case BOOT_DEVICE_FLEXSPI_NOR:
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fuse_fip_offset += NXP_FLEXSPI_FLASH_ADDR;
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break;
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#endif
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default:
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break;
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}
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fuse_fip_block_spec.offset = fuse_fip_offset;
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return io_result;
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}
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int fip_fuse_provisioning(uintptr_t image_buf, uint32_t size)
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{
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uint32_t bit_num;
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uint32_t *gpio_base_addr = NULL;
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struct fuse_hdr_t *fuse_hdr = NULL;
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uint8_t barker[] = {0x68U, 0x39U, 0x27U, 0x81U};
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int ret = -1;
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if (sfp_check_oem_wp() == 0) {
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ret = load_img(FUSE_PROV_IMAGE_ID, &image_buf, &size);
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if (ret != 0) {
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ERROR("Failed to load FUSE PRIV image\n");
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assert(ret == 0);
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}
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fuse_hdr = (struct fuse_hdr_t *)image_buf;
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/* Check barker code */
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if (memcmp(fuse_hdr->barker, barker, sizeof(barker)) != 0) {
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ERROR("FUSE Barker code mismatch.\n");
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error_handler(ERROR_FUSE_BARKER);
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return 1;
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}
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/* Check if GPIO pin to be set for POVDD */
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if (((fuse_hdr->flags >> FLAG_POVDD_SHIFT) & 0x1) != 0) {
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gpio_base_addr =
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select_gpio_n_bitnum(fuse_hdr->povdd_gpio,
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&bit_num);
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/*
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* Add delay so that Efuse gets the power
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* when GPIO is enabled.
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*/
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ret = set_gpio_bit(gpio_base_addr, bit_num);
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mdelay(EFUSE_POWERUP_DELAY_mSec);
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} else {
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ret = (board_enable_povdd() == true) ? 0 : PLAT_ERROR_ENABLE_POVDD;
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}
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if (ret != 0) {
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ERROR("Error enabling board POVDD: %d\n", ret);
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ERROR("Only SFP mirror register will be set.\n");
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}
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provision_fuses(image_buf, ret == 0);
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/* Check if GPIO pin to be reset for POVDD */
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if (((fuse_hdr->flags >> FLAG_POVDD_SHIFT) & 0x1) != 0) {
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if (gpio_base_addr == NULL) {
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gpio_base_addr =
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select_gpio_n_bitnum(
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fuse_hdr->povdd_gpio,
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&bit_num);
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}
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ret = clr_gpio_bit(gpio_base_addr, bit_num);
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} else {
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ret = board_disable_povdd() ? 0 : PLAT_ERROR_DISABLE_POVDD;
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}
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if (ret != 0) {
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ERROR("Error disabling board POVDD: %d\n", ret);
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}
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}
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return 0;
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}
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