392 lines
17 KiB
C
392 lines
17 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEMCTRLV2_H__
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#define __MEMCTRLV2_H__
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#include <mmio.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* StreamID to indicate no SMMU translations (requests to be steered on the
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* SMMU bypass path)
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******************************************************************************/
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#define MC_STREAM_ID_MAX 0x7F
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/*******************************************************************************
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* Stream ID Override Config registers
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******************************************************************************/
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#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0
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#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x70
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#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xA8
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#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xB0
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xE0
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#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xF8
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#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158
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#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188
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#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
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#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8
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#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
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#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8
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#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220
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#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230
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#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268
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#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0
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#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8
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#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0
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#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338
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#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360
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#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368
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#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8
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#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0
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#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8
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#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0
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#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8
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#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400
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#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408
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#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420
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#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428
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#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430
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#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438
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#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440
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#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448
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#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460
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#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468
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#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470
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#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478
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#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480
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#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488
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#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490
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#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498
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#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0
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#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8
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#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0
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#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8
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#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0
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#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8
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#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0
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#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8
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#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0
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#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8
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#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0
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#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8
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#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500
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#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508
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#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518
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/*******************************************************************************
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* Stream ID Security Config registers
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******************************************************************************/
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#define MC_STREAMID_SECURITY_CFG_PTCR 0x4
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#define MC_STREAMID_SECURITY_CFG_AFIR 0x74
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#define MC_STREAMID_SECURITY_CFG_HDAR 0xAC
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#define MC_STREAMID_SECURITY_CFG_HOST1XDMAR 0xB4
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#define MC_STREAMID_SECURITY_CFG_NVENCSRD 0xE4
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#define MC_STREAMID_SECURITY_CFG_SATAR 0xFC
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#define MC_STREAMID_SECURITY_CFG_HDAW 0x1AC
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#define MC_STREAMID_SECURITY_CFG_MPCORER 0x13C
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#define MC_STREAMID_SECURITY_CFG_NVENCSWR 0x15C
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#define MC_STREAMID_SECURITY_CFG_AFIW 0x18C
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#define MC_STREAMID_SECURITY_CFG_MPCOREW 0x1CC
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#define MC_STREAMID_SECURITY_CFG_SATAW 0x1EC
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#define MC_STREAMID_SECURITY_CFG_ISPRA 0x224
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#define MC_STREAMID_SECURITY_CFG_ISPWA 0x234
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#define MC_STREAMID_SECURITY_CFG_ISPWB 0x23C
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#define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR 0x254
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#define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW 0x25C
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#define MC_STREAMID_SECURITY_CFG_XUSB_DEVR 0x264
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#define MC_STREAMID_SECURITY_CFG_XUSB_DEVW 0x26C
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#define MC_STREAMID_SECURITY_CFG_TSECSRD 0x2A4
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#define MC_STREAMID_SECURITY_CFG_TSECSWR 0x2AC
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#define MC_STREAMID_SECURITY_CFG_GPUSRD 0x2C4
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#define MC_STREAMID_SECURITY_CFG_GPUSWR 0x2CC
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#define MC_STREAMID_SECURITY_CFG_SDMMCRA 0x304
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#define MC_STREAMID_SECURITY_CFG_SDMMCRAA 0x30C
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#define MC_STREAMID_SECURITY_CFG_SDMMCR 0x314
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#define MC_STREAMID_SECURITY_CFG_SDMMCRAB 0x31C
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#define MC_STREAMID_SECURITY_CFG_SDMMCWA 0x324
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#define MC_STREAMID_SECURITY_CFG_SDMMCWAA 0x32C
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#define MC_STREAMID_SECURITY_CFG_SDMMCW 0x334
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#define MC_STREAMID_SECURITY_CFG_SDMMCWAB 0x33C
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#define MC_STREAMID_SECURITY_CFG_VICSRD 0x364
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#define MC_STREAMID_SECURITY_CFG_VICSWR 0x36C
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#define MC_STREAMID_SECURITY_CFG_VIW 0x394
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#define MC_STREAMID_SECURITY_CFG_NVDECSRD 0x3C4
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#define MC_STREAMID_SECURITY_CFG_NVDECSWR 0x3CC
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#define MC_STREAMID_SECURITY_CFG_APER 0x3D4
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#define MC_STREAMID_SECURITY_CFG_APEW 0x3DC
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#define MC_STREAMID_SECURITY_CFG_NVJPGSRD 0x3F4
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#define MC_STREAMID_SECURITY_CFG_NVJPGSWR 0x3FC
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#define MC_STREAMID_SECURITY_CFG_SESRD 0x404
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#define MC_STREAMID_SECURITY_CFG_SESWR 0x40C
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#define MC_STREAMID_SECURITY_CFG_ETRR 0x424
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#define MC_STREAMID_SECURITY_CFG_ETRW 0x42C
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#define MC_STREAMID_SECURITY_CFG_TSECSRDB 0x434
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#define MC_STREAMID_SECURITY_CFG_TSECSWRB 0x43C
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#define MC_STREAMID_SECURITY_CFG_GPUSRD2 0x444
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#define MC_STREAMID_SECURITY_CFG_GPUSWR2 0x44C
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#define MC_STREAMID_SECURITY_CFG_AXISR 0x464
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#define MC_STREAMID_SECURITY_CFG_AXISW 0x46C
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#define MC_STREAMID_SECURITY_CFG_EQOSR 0x474
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#define MC_STREAMID_SECURITY_CFG_EQOSW 0x47C
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#define MC_STREAMID_SECURITY_CFG_UFSHCR 0x484
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#define MC_STREAMID_SECURITY_CFG_UFSHCW 0x48C
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#define MC_STREAMID_SECURITY_CFG_NVDISPLAYR 0x494
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#define MC_STREAMID_SECURITY_CFG_BPMPR 0x49C
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#define MC_STREAMID_SECURITY_CFG_BPMPW 0x4A4
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#define MC_STREAMID_SECURITY_CFG_BPMPDMAR 0x4AC
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#define MC_STREAMID_SECURITY_CFG_BPMPDMAW 0x4B4
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#define MC_STREAMID_SECURITY_CFG_AONR 0x4BC
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#define MC_STREAMID_SECURITY_CFG_AONW 0x4C4
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#define MC_STREAMID_SECURITY_CFG_AONDMAR 0x4CC
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#define MC_STREAMID_SECURITY_CFG_AONDMAW 0x4D4
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#define MC_STREAMID_SECURITY_CFG_SCER 0x4DC
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#define MC_STREAMID_SECURITY_CFG_SCEW 0x4E4
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#define MC_STREAMID_SECURITY_CFG_SCEDMAR 0x4EC
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#define MC_STREAMID_SECURITY_CFG_SCEDMAW 0x4F4
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#define MC_STREAMID_SECURITY_CFG_APEDMAR 0x4FC
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#define MC_STREAMID_SECURITY_CFG_APEDMAW 0x504
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#define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1 0x50C
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#define MC_STREAMID_SECURITY_CFG_VICSRD1 0x514
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#define MC_STREAMID_SECURITY_CFG_NVDECSRD1 0x51C
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/*******************************************************************************
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* Memory Controller SMMU Bypass config register
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******************************************************************************/
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#define MC_SMMU_BYPASS_CONFIG 0x1820
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#define MC_SMMU_BYPASS_CTRL_MASK 0x3
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#define MC_SMMU_BYPASS_CTRL_SHIFT 0
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#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31)
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#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
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MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
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/*******************************************************************************
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* Memory Controller transaction override config registers
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******************************************************************************/
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#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8
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#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0
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#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000
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#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490
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#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478
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#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8
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#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328
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#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360
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#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8
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#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0
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#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460
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#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330
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#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470
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#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8
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#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318
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#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510
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#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8
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#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308
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#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468
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#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260
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#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480
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#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8
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#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8
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#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8
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#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258
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#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438
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#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440
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#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8
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#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448
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#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0
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#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500
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#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0
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#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0
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#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420
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#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408
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#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0
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#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0
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#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430
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#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0
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#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0
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#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518
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#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250
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#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230
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#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400
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#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8
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#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8
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#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320
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#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8
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#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8
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#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488
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#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8
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#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8
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#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428
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#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368
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#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158
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#define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300
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#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508
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#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238
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#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498
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#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8
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#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310
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#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268
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#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0
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#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188
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#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0
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/*******************************************************************************
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* Non-SO_DEV transactions override values for CGID_TAG bitfield for the
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* MC_TXN_OVERRIDE_CONFIG_{module} registers
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******************************************************************************/
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#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0
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#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1
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#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2
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#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3
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#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3
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/*******************************************************************************
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* Structure to hold the transaction override settings to use to override
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* client inputs
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******************************************************************************/
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typedef struct mc_txn_override_cfg {
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uint32_t offset;
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uint8_t cgid_tag;
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} mc_txn_override_cfg_t;
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#define mc_make_txn_override_cfg(off, val) \
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{ \
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.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
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.cgid_tag = MC_TXN_OVERRIDE_ ## val \
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}
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/*******************************************************************************
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* Structure to hold the Stream ID to use to override client inputs
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******************************************************************************/
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typedef struct mc_streamid_override_cfg {
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uint32_t offset;
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uint8_t stream_id;
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} mc_streamid_override_cfg_t;
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/*******************************************************************************
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* Structure to hold the Stream ID Security Configuration settings
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******************************************************************************/
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typedef struct mc_streamid_security_cfg {
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char *name;
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uint32_t offset;
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int override_enable;
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int override_client_inputs;
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int override_client_ns_flag;
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} mc_streamid_security_cfg_t;
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#define OVERRIDE_DISABLE 1
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#define OVERRIDE_ENABLE 0
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#define CLIENT_FLAG_SECURE 0
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#define CLIENT_FLAG_NON_SECURE 1
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#define CLIENT_INPUTS_OVERRIDE 1
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#define CLIENT_INPUTS_NO_OVERRIDE 0
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|
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#define mc_make_sec_cfg(off, ns, ovrrd, access) \
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|
{ \
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|
.name = # off, \
|
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.offset = MC_STREAMID_SECURITY_CFG_ ## off, \
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.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
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.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
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|
.override_enable = OVERRIDE_ ## access \
|
|
}
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|
|
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/*******************************************************************************
|
|
* TZDRAM carveout configuration registers
|
|
******************************************************************************/
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|
#define MC_SECURITY_CFG0_0 0x70
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|
#define MC_SECURITY_CFG1_0 0x74
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#define MC_SECURITY_CFG3_0 0x9BC
|
|
|
|
/*******************************************************************************
|
|
* Video Memory carveout configuration registers
|
|
******************************************************************************/
|
|
#define MC_VIDEO_PROTECT_BASE_HI 0x978
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|
#define MC_VIDEO_PROTECT_BASE_LO 0x648
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|
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
|
|
|
|
/*******************************************************************************
|
|
* TZRAM carveout configuration registers
|
|
******************************************************************************/
|
|
#define MC_TZRAM_BASE 0x1850
|
|
#define MC_TZRAM_END 0x1854
|
|
#define MC_TZRAM_HI_ADDR_BITS 0x1588
|
|
#define TZRAM_ADDR_HI_BITS_MASK 0x3
|
|
#define TZRAM_END_HI_BITS_SHIFT 8
|
|
#define MC_TZRAM_REG_CTRL 0x185c
|
|
#define DISABLE_TZRAM_ACCESS 1
|
|
|
|
static inline uint32_t tegra_mc_read_32(uint32_t off)
|
|
{
|
|
return mmio_read_32(TEGRA_MC_BASE + off);
|
|
}
|
|
|
|
static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
|
|
{
|
|
mmio_write_32(TEGRA_MC_BASE + off, val);
|
|
}
|
|
|
|
static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
|
|
{
|
|
return mmio_read_32(TEGRA_MC_STREAMID_BASE + off);
|
|
}
|
|
|
|
static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
|
|
{
|
|
mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
|
|
}
|
|
|
|
#endif /* __MEMCTRLV2_H__ */
|