359 lines
14 KiB
C
359 lines
14 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MCE_H__
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#define __MCE_H__
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#include <mmio.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* MCE apertures used by the ARI interface
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*
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* Aperture 0 - Cpu0 (ARM Cortex A-57)
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* Aperture 1 - Cpu1 (ARM Cortex A-57)
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* Aperture 2 - Cpu2 (ARM Cortex A-57)
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* Aperture 3 - Cpu3 (ARM Cortex A-57)
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* Aperture 4 - Cpu4 (Denver15)
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* Aperture 5 - Cpu5 (Denver15)
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******************************************************************************/
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#define MCE_ARI_APERTURE_0_OFFSET 0x0
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#define MCE_ARI_APERTURE_1_OFFSET 0x10000
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#define MCE_ARI_APERTURE_2_OFFSET 0x20000
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#define MCE_ARI_APERTURE_3_OFFSET 0x30000
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#define MCE_ARI_APERTURE_4_OFFSET 0x40000
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#define MCE_ARI_APERTURE_5_OFFSET 0x50000
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#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
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/* number of apertures */
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#define MCE_ARI_APERTURES_MAX 6
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/* each ARI aperture is 64KB */
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#define MCE_ARI_APERTURE_SIZE 0x10000
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/*******************************************************************************
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* CPU core ids - used by the MCE_ONLINE_CORE ARI
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******************************************************************************/
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typedef enum mce_core_id {
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MCE_CORE_ID_DENVER_15_0,
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MCE_CORE_ID_DENVER_15_1,
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/* 2 and 3 are reserved */
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MCE_CORE_ID_A57_0 = 4,
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MCE_CORE_ID_A57_1,
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MCE_CORE_ID_A57_2,
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MCE_CORE_ID_A57_3,
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MCE_CORE_ID_MAX
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} mce_core_id_t;
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#define MCE_CORE_ID_MASK 0x7
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/*******************************************************************************
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* MCE commands
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******************************************************************************/
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typedef enum mce_cmd {
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MCE_CMD_ENTER_CSTATE = 0,
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MCE_CMD_UPDATE_CSTATE_INFO,
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MCE_CMD_UPDATE_CROSSOVER_TIME,
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MCE_CMD_READ_CSTATE_STATS,
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MCE_CMD_WRITE_CSTATE_STATS,
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MCE_CMD_IS_SC7_ALLOWED,
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MCE_CMD_ONLINE_CORE,
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MCE_CMD_CC3_CTRL,
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MCE_CMD_ECHO_DATA,
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MCE_CMD_READ_VERSIONS,
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MCE_CMD_ENUM_FEATURES,
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MCE_CMD_ROC_FLUSH_CACHE_TRBITS,
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MCE_CMD_ENUM_READ_MCA,
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MCE_CMD_ENUM_WRITE_MCA,
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MCE_CMD_ROC_FLUSH_CACHE,
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MCE_CMD_ROC_CLEAN_CACHE,
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MCE_CMD_IS_CCX_ALLOWED = 0xFE,
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MCE_CMD_MAX = 0xFF,
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} mce_cmd_t;
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#define MCE_CMD_MASK 0xFF
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/*******************************************************************************
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* Macros to prepare CSTATE info request
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******************************************************************************/
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/* Description of the parameters for UPDATE_CSTATE_INFO request */
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#define CLUSTER_CSTATE_MASK 0x7
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#define CLUSTER_CSTATE_SHIFT 0
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#define CLUSTER_CSTATE_UPDATE_BIT (1 << 7)
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#define CCPLEX_CSTATE_MASK 0x3
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#define CCPLEX_CSTATE_SHIFT 8
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#define CCPLEX_CSTATE_UPDATE_BIT (1 << 15)
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#define SYSTEM_CSTATE_MASK 0xF
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#define SYSTEM_CSTATE_SHIFT 16
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#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22
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#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22)
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#define SYSTEM_CSTATE_UPDATE_BIT (1 << 23)
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#define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31)
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#define CSTATE_WAKE_MASK_SHIFT 32
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#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF
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/*******************************************************************************
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* Auto-CC3 control macros
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******************************************************************************/
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#define MCE_AUTO_CC3_FREQ_MASK 0x1FF
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#define MCE_AUTO_CC3_FREQ_SHIFT 0
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#define MCE_AUTO_CC3_VTG_MASK 0x7F
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#define MCE_AUTO_CC3_VTG_SHIFT 16
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#define MCE_AUTO_CC3_ENABLE_BIT (1 << 31)
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/*******************************************************************************
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* Macros for the 'IS_SC7_ALLOWED' command
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******************************************************************************/
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#define MCE_SC7_ALLOWED_MASK 0x7
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#define MCE_SC7_WAKE_TIME_SHIFT 32
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/*******************************************************************************
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* Macros for 'read/write ctats' commands
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******************************************************************************/
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#define MCE_CSTATE_STATS_TYPE_SHIFT 32
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#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF
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/*******************************************************************************
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* Macros for 'update crossover threshold' command
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******************************************************************************/
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#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32
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/*******************************************************************************
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* Timeout value used to powerdown a core
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******************************************************************************/
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#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
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/*******************************************************************************
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* MCA command struct
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******************************************************************************/
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typedef union mca_cmd {
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struct command {
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uint8_t cmd;
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uint8_t idx;
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uint8_t subidx;
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} command;
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struct input {
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uint32_t low;
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uint32_t high;
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} input;
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uint64_t data;
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} mca_cmd_t;
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/*******************************************************************************
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* MCA argument struct
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******************************************************************************/
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typedef union mca_arg {
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struct err {
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uint64_t error:8;
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uint64_t unused:48;
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uint64_t finish:8;
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} err;
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struct arg {
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uint32_t low;
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uint32_t high;
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} arg;
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uint64_t data;
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} mca_arg_t;
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/*******************************************************************************
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* Structure populated by arch specific code to export routines which perform
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* common low level MCE functions
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******************************************************************************/
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typedef struct arch_mce_ops {
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/*
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* This ARI request sets up the MCE to start execution on assertion
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* of STANDBYWFI, update the core power state and expected wake time,
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* then determine the proper power state to enter.
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*/
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int (*enter_cstate)(uint32_t ari_base, uint32_t state,
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uint32_t wake_time);
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/*
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* This ARI request allows updating of the CLUSTER_CSTATE,
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* CCPLEX_CSTATE, and SYSTEM_CSTATE register values.
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*/
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int (*update_cstate_info)(uint32_t ari_base,
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uint32_t cluster,
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uint32_t ccplex,
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uint32_t system,
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uint8_t sys_state_force,
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uint32_t wake_mask,
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uint8_t update_wake_mask);
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/*
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* This ARI request allows updating of power state crossover
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* threshold times. An index value specifies which crossover
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* state is being updated.
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*/
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int (*update_crossover_time)(uint32_t ari_base,
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uint32_t type,
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uint32_t time);
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/*
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* This ARI request allows read access to statistical information
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* related to power states.
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*/
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uint64_t (*read_cstate_stats)(uint32_t ari_base,
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uint32_t state);
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/*
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* This ARI request allows write access to statistical information
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* related to power states.
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*/
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int (*write_cstate_stats)(uint32_t ari_base,
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uint32_t state,
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uint32_t stats);
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/*
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* This ARI request allows the CPU to understand the features
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* supported by the MCE firmware.
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*/
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uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd,
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uint32_t data);
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/*
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* This ARI request allows querying the CCPLEX to determine if
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* the CCx state is allowed given a target core C-state and wake
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* time. If the CCx state is allowed, the response indicates CCx
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* must be entered. If the CCx state is not allowed, the response
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* indicates CC6/CC7 can't be entered
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*/
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int (*is_ccx_allowed)(uint32_t ari_base, uint32_t state,
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uint32_t wake_time);
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/*
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* This ARI request allows querying the CCPLEX to determine if
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* the SC7 state is allowed given a target core C-state and wake
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* time. If the SC7 state is allowed, all cores but the associated
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* core are offlined (WAKE_EVENTS are set to 0) and the response
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* indicates SC7 must be entered. If the SC7 state is not allowed,
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* the response indicates SC7 can't be entered
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*/
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int (*is_sc7_allowed)(uint32_t ari_base, uint32_t state,
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uint32_t wake_time);
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/*
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* This ARI request allows a core to bring another offlined core
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* back online to the C0 state. Note that a core is offlined by
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* entering a C-state where the WAKE_MASK is all 0.
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*/
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int (*online_core)(uint32_t ari_base, uint32_t cpuid);
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/*
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* This ARI request allows the CPU to enable/disable Auto-CC3 idle
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* state.
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*/
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int (*cc3_ctrl)(uint32_t ari_base,
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uint32_t freq,
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uint32_t volt,
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uint8_t enable);
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/*
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* This ARI request allows updating the reset vector register for
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* D15 and A57 CPUs.
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*/
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int (*update_reset_vector)(uint32_t ari_base,
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uint32_t addr_low,
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uint32_t addr_high);
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/*
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* This ARI request instructs the ROC to flush A57 data caches in
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* order to maintain coherency with the Denver cluster.
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*/
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int (*roc_flush_cache)(uint32_t ari_base);
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/*
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* This ARI request instructs the ROC to flush A57 data caches along
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* with the caches covering ARM code in order to maintain coherency
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* with the Denver cluster.
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*/
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int (*roc_flush_cache_trbits)(uint32_t ari_base);
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/*
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* This ARI request instructs the ROC to clean A57 data caches along
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* with the caches covering ARM code in order to maintain coherency
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* with the Denver cluster.
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*/
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int (*roc_clean_cache)(uint32_t ari_base);
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/*
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* This ARI request reads/writes the Machine Check Arch. (MCA)
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* registers.
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*/
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uint64_t (*read_write_mca)(uint32_t ari_base,
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mca_cmd_t cmd,
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uint64_t *data);
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/*
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* Some MC GSC (General Security Carveout) register values are
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* expected to be changed by TrustZone secure ARM code after boot.
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* Since there is no hardware mechanism for the CCPLEX to know
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* that an MC GSC register has changed to allow it to update its
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* own internal GSC register, there needs to be a mechanism that
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* can be used by ARM code to cause the CCPLEX to update its GSC
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* register value. This ARI request allows updating the GSC register
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* value for a certain carveout in the CCPLEX.
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*/
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int (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx);
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/*
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* This ARI request instructs the CCPLEX to either shutdown or
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* reset the entire system
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*/
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void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx);
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} arch_mce_ops_t;
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int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
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uint64_t arg2);
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int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi);
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int mce_update_gsc_videomem(void);
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int mce_update_gsc_tzdram(void);
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int mce_update_gsc_tzram(void);
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__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
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/* declarations for ARI/NVG handler functions */
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int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
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uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
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uint8_t update_wake_mask);
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int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
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uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state);
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int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats);
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uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data);
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int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int ari_online_core(uint32_t ari_base, uint32_t core);
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int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
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int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi);
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int ari_roc_flush_cache_trbits(uint32_t ari_base);
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int ari_roc_flush_cache(uint32_t ari_base);
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int ari_roc_clean_cache(uint32_t ari_base);
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uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data);
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int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx);
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void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx);
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int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
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uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
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uint8_t update_wake_mask);
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int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
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uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state);
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int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val);
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int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int nvg_online_core(uint32_t ari_base, uint32_t core);
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int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
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#endif /* __MCE_H__ */
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