172 lines
5.5 KiB
C
172 lines
5.5 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <errno.h>
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#include <mce.h>
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#include <memctrl.h>
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#include <runtime_svc.h>
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#include <t18x_ari.h>
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#include <tegra_private.h>
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extern uint32_t tegra186_system_powerdn_state;
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/*******************************************************************************
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* Tegra186 SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
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#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01
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#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00
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#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01
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#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02
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#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03
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#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04
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#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05
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#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06
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#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07
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#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08
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#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09
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#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A
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#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B
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#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C
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#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D
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#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E
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#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F
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/*******************************************************************************
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* This function is responsible for handling all T186 SiP calls
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******************************************************************************/
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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int mce_ret;
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switch (smc_fid) {
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/*
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* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
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* 0x82FFFFFF SiP SMC space
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*/
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case TEGRA_SIP_MCE_CMD_ENTER_CSTATE:
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case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO:
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case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME:
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case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS:
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case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS:
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case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED:
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case TEGRA_SIP_MCE_CMD_CC3_CTRL:
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case TEGRA_SIP_MCE_CMD_ECHO_DATA:
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case TEGRA_SIP_MCE_CMD_READ_VERSIONS:
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case TEGRA_SIP_MCE_CMD_ENUM_FEATURES:
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case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
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case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA:
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case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
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case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
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case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
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/* clean up the high bits */
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smc_fid &= MCE_CMD_MASK;
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/* execute the command and store the result */
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mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret);
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return 0;
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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/* clean up the high bits */
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x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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/*
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* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
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* or falls outside of the valid DRAM range
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*/
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mce_ret = bl31_check_ns_address(x1, x2);
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if (mce_ret)
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return -ENOTSUP;
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/*
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* Check if Video Memory is aligned to 1MB.
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*/
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if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
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ERROR("Unaligned Video Memory base address!\n");
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return -ENOTSUP;
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}
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/* new video memory carveout settings */
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tegra_memctrl_videomem_setup(x1, x2);
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return 0;
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case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE:
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/* clean up the high bits */
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x1 = (uint32_t)x1;
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/*
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* SC8 is a special Tegra186 system state where the CPUs and
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* DRAM are powered down but the other subsystem is still
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* alive.
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*/
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if ((x1 == TEGRA_ARI_SYSTEM_SC8) ||
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(x1 == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF)) {
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tegra186_system_powerdn_state = x1;
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flush_dcache_range(
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(uintptr_t)&tegra186_system_powerdn_state,
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sizeof(tegra186_system_powerdn_state));
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} else {
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ERROR("%s: unhandled powerdn state (%d)\n", __func__,
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(uint32_t)x1);
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return -ENOTSUP;
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}
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return 0;
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default:
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break;
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}
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return -ENOTSUP;
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}
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