150 lines
4.0 KiB
C
150 lines
4.0 KiB
C
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include <dcfg_lsch3.h>
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#include <soc_default_base_addr.h>
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#include <soc_default_helper_macros.h>
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/*
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* SVR Definition of LS1028A
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* (not include major and minor rev)
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* These info is listed in Table B-6. DCFG differences
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* between LS1028A and LS1027A of LS1028ARM(Reference Manual)
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*/
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#define SVR_LS1017AN 0x870B25
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#define SVR_LS1017AE 0x870B24
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#define SVR_LS1018AN 0x870B21
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#define SVR_LS1018AE 0x870B20
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#define SVR_LS1027AN 0x870B05
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#define SVR_LS1027AE 0x870B04
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#define SVR_LS1028AN 0x870B01
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#define SVR_LS1028AE 0x870B00
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/* Number of cores in platform */
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#define PLATFORM_CORE_COUNT 2
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#define NUMBER_OF_CLUSTERS 1
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#define CORES_PER_CLUSTER 2
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/* Set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS 1
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#define NUM_DRAM_REGIONS 3
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#define NXP_DRAM0_ADDR 0x80000000
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#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2GB */
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#define NXP_DRAM1_ADDR 0x2080000000
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#define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126G */
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#define NXP_DRAM2_ADDR 0x6000000000
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#define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */
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/* DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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/* CCSR space memory Map */
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#undef NXP_UART_ADDR
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#define NXP_UART_ADDR 0x021C0500
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#undef NXP_UART1_ADDR
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#define NXP_UART1_ADDR 0x021C0600
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#undef NXP_WDOG1_TZ_ADDR
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#define NXP_WDOG1_TZ_ADDR 0x023C0000
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#undef NXP_GICR_ADDR
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#define NXP_GICR_ADDR 0x06040000
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#undef NXP_GICR_SGI_ADDR
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#define NXP_GICR_SGI_ADDR 0x06050000
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/* EPU register offsets and values */
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#define EPU_EPGCR_OFFSET 0x0
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#define EPU_EPIMCR10_OFFSET 0x128
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#define EPU_EPCTR10_OFFSET 0xa28
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#define EPU_EPCCR10_OFFSET 0x828
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#define EPU_EPCCR10_VAL 0xb2800000
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#define EPU_EPIMCR10_VAL 0xba000000
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#define EPU_EPCTR10_VAL 0x0
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#define EPU_EPGCR_VAL (1 << 31)
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/* PORSR1 */
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#define PORSR1_RCW_MASK 0x07800000
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#define PORSR1_RCW_SHIFT 23
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#define SDHC1_VAL 0x8
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#define SDHC2_VAL 0x9
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#define I2C1_VAL 0xa
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#define FLEXSPI_NAND2K_VAL 0xc
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#define FLEXSPI_NAND4K_VAL 0xd
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#define FLEXSPI_NOR 0xf
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/*
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* Required LS standard platform porting definitions
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* for CCI-400
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*/
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#define NXP_CCI_CLUSTER0_SL_IFACE_IX 4
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40)
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/* Clock Divisors */
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#define NXP_PLATFORM_CLK_DIVIDER 1
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#define NXP_UART_CLK_DIVIDER 2
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/* dcfg register offsets and values */
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#define DCFG_DEVDISR2_ENETC (1 << 31)
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#define MPIDR_AFFINITY0_MASK 0x00FF
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#define MPIDR_AFFINITY1_MASK 0xFF00
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#define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000
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#define CPUECTLR_INS_PREFETCH_MASK 0x1800000000
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#define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000
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#define OSDLR_EL1_DLK_LOCK 0x1
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#define CNTP_CTL_EL0_EN 0x1
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#define CNTP_CTL_EL0_IMASK 0x2
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#define SYSTEM_PWR_DOMAINS 1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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NUMBER_OF_CLUSTERS + \
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SYSTEM_PWR_DOMAINS)
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/* Power state coordination occurs at the system level */
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#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
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/* Local power state for power domains in Run state */
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#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
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/* define retention state */
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
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#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
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/* define power-down state */
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
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#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
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/* One cache line needed for bakery locks on ARM platforms */
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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#ifndef __ASSEMBLER__
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/* CCI slave interfaces */
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static const int cci_map[] = {
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NXP_CCI_CLUSTER0_SL_IFACE_IX,
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};
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void soc_init_lowlevel(void);
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void soc_init_percpu(void);
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void _soc_set_start_addr(unsigned long addr);
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void _set_platform_security(void);
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#endif
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#endif /* SOC_H */
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