123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <mmio.h>
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#include <mt8173_def.h>
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#include <mtcmos.h>
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#include <spm.h>
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enum {
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SRAM_ISOINT_B = 1U << 6,
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SRAM_CKISO = 1U << 5,
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PWR_CLK_DIS = 1U << 4,
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PWR_ON_2ND = 1U << 3,
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PWR_ON = 1U << 2,
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PWR_ISO = 1U << 1,
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PWR_RST_B = 1U << 0
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};
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enum {
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L1_PDN_ACK = 1U << 8,
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L1_PDN = 1U << 0
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};
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enum {
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LITTLE_CPU3 = 1U << 12,
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LITTLE_CPU2 = 1U << 11,
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LITTLE_CPU1 = 1U << 10,
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};
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enum {
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SRAM_PDN = 0xf << 8,
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DIS_SRAM_ACK = 0x1 << 12,
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AUD_SRAM_ACK = 0xf << 12,
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};
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enum {
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DIS_PWR_STA_MASK = 0x1 << 3,
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AUD_PWR_STA_MASK = 0x1 << 24,
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};
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static void mtcmos_ctrl_little_off(unsigned int linear_id)
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{
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uint32_t reg_pwr_con;
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uint32_t reg_l1_pdn;
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uint32_t bit_cpu;
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switch (linear_id) {
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case 1:
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reg_pwr_con = SPM_CA7_CPU1_PWR_CON;
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reg_l1_pdn = SPM_CA7_CPU1_L1_PDN;
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bit_cpu = LITTLE_CPU1;
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break;
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case 2:
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reg_pwr_con = SPM_CA7_CPU2_PWR_CON;
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reg_l1_pdn = SPM_CA7_CPU2_L1_PDN;
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bit_cpu = LITTLE_CPU2;
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break;
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case 3:
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reg_pwr_con = SPM_CA7_CPU3_PWR_CON;
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reg_l1_pdn = SPM_CA7_CPU3_L1_PDN;
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bit_cpu = LITTLE_CPU3;
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break;
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default:
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/* should never come to here */
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return;
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}
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/* enable register control */
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mmio_write_32(SPM_POWERON_CONFIG_SET,
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(SPM_PROJECT_CODE << 16) | (1U << 0));
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mmio_setbits_32(reg_pwr_con, PWR_ISO);
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mmio_setbits_32(reg_pwr_con, SRAM_CKISO);
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mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B);
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mmio_setbits_32(reg_l1_pdn, L1_PDN);
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while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK))
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continue;
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mmio_clrbits_32(reg_pwr_con, PWR_RST_B);
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mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS);
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mmio_clrbits_32(reg_pwr_con, PWR_ON);
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mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND);
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while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) ||
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(mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu))
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continue;
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}
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void mtcmos_little_cpu_off(void)
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{
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/* turn off little cpu 1 - 3 */
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mtcmos_ctrl_little_off(1);
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mtcmos_ctrl_little_off(2);
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mtcmos_ctrl_little_off(3);
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}
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