23 lines
708 B
C
23 lines
708 B
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_A55_H__
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#define __CORTEX_A55_H__
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/* Cortex-A55 MIDR for revision 0 */
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#define CORTEX_A55_MIDR 0x410fd050
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4
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/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
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#define CORTEX_A55_CORE_PWRDN_EN_MASK 0x1
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#endif /* __CORTEX_A55_H__ */
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