184 lines
4.6 KiB
ArmAsm
184 lines
4.6 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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.globl get_afflvl_shift
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.globl mpidr_mask_lower_afflvls
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.globl eret
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.globl smc
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.globl zeromem16
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.globl memcpy16
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.globl disable_mmu_el3
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.globl disable_mmu_icache_el3
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#if SUPPORT_VFP
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.globl enable_vfp
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#endif
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func get_afflvl_shift
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cmp x0, #3
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cinc x0, x0, eq
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mov x1, #MPIDR_AFFLVL_SHIFT
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lsl x0, x0, x1
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ret
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endfunc get_afflvl_shift
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func mpidr_mask_lower_afflvls
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cmp x1, #3
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cinc x1, x1, eq
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mov x2, #MPIDR_AFFLVL_SHIFT
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lsl x2, x1, x2
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lsr x0, x0, x2
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lsl x0, x0, x2
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ret
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endfunc mpidr_mask_lower_afflvls
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func eret
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eret
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endfunc eret
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func smc
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smc #0
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endfunc smc
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/* -----------------------------------------------------------------------
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* void zeromem16(void *mem, unsigned int length);
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*
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* Initialise a memory region to 0.
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* The memory address must be 16-byte aligned.
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* -----------------------------------------------------------------------
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*/
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func zeromem16
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#if ASM_ASSERTION
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tst x0, #0xf
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ASM_ASSERT(eq)
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#endif
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add x2, x0, x1
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/* zero 16 bytes at a time */
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z_loop16:
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sub x3, x2, x0
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cmp x3, #16
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b.lt z_loop1
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stp xzr, xzr, [x0], #16
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b z_loop16
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/* zero byte per byte */
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z_loop1:
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cmp x0, x2
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b.eq z_end
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strb wzr, [x0], #1
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b z_loop1
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z_end:
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ret
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endfunc zeromem16
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/* --------------------------------------------------------------------------
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* void memcpy16(void *dest, const void *src, unsigned int length)
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*
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* Copy length bytes from memory area src to memory area dest.
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* The memory areas should not overlap.
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* Destination and source addresses must be 16-byte aligned.
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* --------------------------------------------------------------------------
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*/
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func memcpy16
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#if ASM_ASSERTION
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orr x3, x0, x1
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tst x3, #0xf
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ASM_ASSERT(eq)
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#endif
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/* copy 16 bytes at a time */
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m_loop16:
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cmp x2, #16
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b.lt m_loop1
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b m_loop16
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/* copy byte per byte */
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m_loop1:
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cbz x2, m_end
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne m_loop1
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m_end:
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ret
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endfunc memcpy16
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/* ---------------------------------------------------------------------------
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* Disable the MMU at EL3
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* This is implemented in assembler to ensure that the data cache is cleaned
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* and invalidated after the MMU is disabled without any intervening cacheable
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* data accesses
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* ---------------------------------------------------------------------------
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*/
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func disable_mmu_el3
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
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do_disable_mmu:
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mrs x0, sctlr_el3
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bic x0, x0, x1
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msr sctlr_el3, x0
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isb // ensure MMU is off
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mov x0, #DCCISW // DCache clean and invalidate
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b dcsw_op_all
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endfunc disable_mmu_el3
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func disable_mmu_icache_el3
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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b do_disable_mmu
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endfunc disable_mmu_icache_el3
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/* ---------------------------------------------------------------------------
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* Enable the use of VFP at EL3
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* ---------------------------------------------------------------------------
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*/
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#if SUPPORT_VFP
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func enable_vfp
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mrs x0, cpacr_el1
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orr x0, x0, #CPACR_VFP_BITS
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msr cpacr_el1, x0
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mrs x0, cptr_el3
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mov x1, #AARCH64_CPTR_TFP
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bic x0, x0, x1
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msr cptr_el3, x0
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isb
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ret
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endfunc enable_vfp
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#endif
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