206 lines
6.9 KiB
ArmAsm
206 lines
6.9 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cortex_a57.h>
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#include <cpu_macros.S>
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#include <platform_def.h>
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#include "../juno_def.h"
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_report_exception
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.globl plat_reset_handler
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.globl platform_get_core_pos
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.globl platform_mem_init
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/* Define a crash console for the plaform */
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#define JUNO_CRASH_CONSOLE_BASE PL011_UART3_BASE
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, JUNO_CRASH_CONSOLE_BASE
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mov_imm x1, PL011_UART3_CLK_IN_HZ
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mov_imm x2, PL011_BAUDRATE
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b console_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, JUNO_CRASH_CONSOLE_BASE
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b console_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_report_exception(unsigned int type)
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* Function to report an unhandled exception
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* with platform-specific means.
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* On Juno platform, it updates the LEDs
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* to indicate where we are
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* ---------------------------------------------
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*/
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func plat_report_exception
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mrs x1, CurrentEl
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lsr x1, x1, #MODE_EL_SHIFT
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lsl x1, x1, #SYS_LED_EL_SHIFT
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lsl x0, x0, #SYS_LED_EC_SHIFT
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mov x2, #(SECURE << SYS_LED_SS_SHIFT)
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orr x0, x0, x2
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orr x0, x0, x1
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mov x1, #VE_SYSREGS_BASE
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add x1, x1, #V2M_SYS_LED
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str w0, [x1]
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ret
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endfunc plat_report_exception
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/*
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* Return 0 to 3 for the A53s and 4 or 5 for the A57s
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*/
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func platform_get_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap A53/A57 order
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add x0, x1, x0, LSR #6
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ret
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endfunc platform_get_core_pos
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/* -----------------------------------------------------
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* void platform_mem_init(void);
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*
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* We don't need to carry out any memory initialization
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* on Juno. The Secure RAM is accessible straight away.
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* -----------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* --------------------------------------------------------------------
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* void plat_reset_handler(void);
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*
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* Before adding code in this function, refer to the guidelines in
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* docs/firmware-design.md to determine whether the code should reside
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* within the FIRST_RESET_HANDLER_CALL block or not.
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*
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* For Juno r0:
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* - Implement workaround for defect id 831273 by enabling an event
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* stream every 65536 cycles.
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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*
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* For Juno r1:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* Note that:
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* - The default value for the L2 Tag RAM latency for Cortex-A57 is
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* suitable.
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* - Defect #831273 doesn't affect Juno r1.
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*
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* This code is included only when FIRST_RESET_HANDLER_CALL is defined
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* since it should be executed only during BL1.
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* --------------------------------------------------------------------
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*/
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func plat_reset_handler
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#ifdef FIRST_RESET_HANDLER_CALL
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/* --------------------------------------------------------------------
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* Determine whether this code is running on Juno r0 or Juno r1.
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* Keep this information in x2.
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* --------------------------------------------------------------------
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*/
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/* Read the V2M SYS_ID register */
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mov_imm x0, (VE_SYSREGS_BASE + V2M_SYS_ID)
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ldr w1, [x0]
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/* Extract board revision from the SYS_ID */
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ubfx x1, x1, #SYS_ID_REV_SHIFT, #4
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/*
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* On Juno R0: x2 := REV_JUNO_R0 - 1 = 0
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* On Juno R1: x2 := REV_JUNO_R1 - 1 = 1
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*/
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sub x2, x1, #1
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/* --------------------------------------------------------------------
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* Determine whether this code is executed on a Cortex-A53 or on a
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* Cortex-A57 core.
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* --------------------------------------------------------------------
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*/
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mrs x0, midr_el1
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ubfx x1, x0, MIDR_PN_SHIFT, #12
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cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq A57
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/* Nothing needs to be done for the Cortex-A53 on Juno r1 */
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cbz x2, apply_831273
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ret
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A57:
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/* --------------------------------------------------------------------
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* Cortex-A57 specific settings
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* --------------------------------------------------------------------
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*/
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/* Change the L2 Data RAM latency to 3 cycles */
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mov x0, #L2_DATA_RAM_LATENCY_3_CYCLES
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cbnz x2, apply_l2_ram_latencies
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/* On Juno r0, also change the L2 Tag RAM latency to 3 cycles */
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orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)
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apply_l2_ram_latencies:
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msr L2CTLR_EL1, x0
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/* Juno r1 doesn't suffer from defect #831273 */
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cbnz x2, ret
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apply_831273:
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/* --------------------------------------------------------------------
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* On Juno r0, enable the event stream every 65536 cycles
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* --------------------------------------------------------------------
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*/
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mov x0, #(0xf << EVNTI_SHIFT)
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orr x0, x0, #EVNTEN_BIT
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msr CNTKCTL_EL1, x0
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ret:
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isb
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#endif /* FIRST_RESET_HANDLER_CALL */
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ret
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endfunc plat_reset_handler
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