362 lines
11 KiB
C
362 lines
11 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
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#include <a8k_common.h>
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#include <ccu.h>
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#include <debug.h>
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#include <mmio.h>
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#include <mvebu.h>
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#include <mvebu_def.h>
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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#define DEBUG_ADDR_MAP
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#endif
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/* common defines */
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#define WIN_ENABLE_BIT (0x1)
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/* Physical address of the base of the window = {AddrLow[19:0],20’h0} */
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#define ADDRESS_SHIFT (20 - 4)
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#define ADDRESS_MASK (0xFFFFFFF0)
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#define CCU_WIN_ALIGNMENT (0x100000)
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#define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \
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((tgt) == DRAM_1_TID) || \
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((tgt) == RAR_TID)) ? 1 : 0)
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/* For storage of CR, SCR, ALR, AHR abd GCR */
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static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1];
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#ifdef DEBUG_ADDR_MAP
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static void dump_ccu(int ap_index)
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{
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uint32_t win_id, win_cr, alr, ahr;
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uint8_t target_id;
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uint64_t start, end;
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/* Dump all AP windows */
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tf_printf("\tbank target start end\n");
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tf_printf("\t----------------------------------------------------\n");
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for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) {
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win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
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if (win_cr & WIN_ENABLE_BIT) {
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target_id = (win_cr >> CCU_TARGET_ID_OFFSET) &
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CCU_TARGET_ID_MASK;
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alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index,
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win_id));
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ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index,
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win_id));
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start = ((uint64_t)alr << ADDRESS_SHIFT);
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end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
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tf_printf("\tccu %02x 0x%016llx 0x%016llx\n",
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target_id, start, end);
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}
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}
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win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index));
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target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK;
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tf_printf("\tccu GCR %d - all other transactions\n", target_id);
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}
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#endif
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void ccu_win_check(struct addr_map_win *win)
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{
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/* check if address is aligned to 1M */
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if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) {
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win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT);
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NOTICE("%s: Align up the base address to 0x%llx\n",
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__func__, win->base_addr);
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}
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/* size parameter validity check */
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if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) {
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win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT);
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NOTICE("%s: Aligning size to 0x%llx\n",
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__func__, win->win_size);
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}
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}
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void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id)
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{
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uint32_t ccu_win_reg;
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uint32_t alr, ahr;
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uint64_t end_addr;
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if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) {
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ERROR("Enabling wrong CCU window %d!\n", win_id);
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return;
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}
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end_addr = (win->base_addr + win->win_size - 1);
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alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
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ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
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mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr);
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mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr);
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ccu_win_reg = WIN_ENABLE_BIT;
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ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK)
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<< CCU_TARGET_ID_OFFSET;
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mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg);
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}
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static void ccu_disable_win(int ap_index, uint32_t win_id)
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{
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uint32_t win_reg;
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if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) {
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ERROR("Disabling wrong CCU window %d!\n", win_id);
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return;
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}
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win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
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win_reg &= ~WIN_ENABLE_BIT;
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mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg);
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}
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/* Insert/Remove temporary window for using the out-of reset default
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* CPx base address to access the CP configuration space prior to
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* the further base address update in accordance with address mapping
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* design.
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*
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* NOTE: Use the same window array for insertion and removal of
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* temporary windows.
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*/
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void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size)
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{
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uint32_t win_id;
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for (int i = 0; i < size; i++) {
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win_id = MVEBU_CCU_MAX_WINS - 1 - i;
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ccu_win_check(win);
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ccu_enable_win(ap_index, win, win_id);
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win++;
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}
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}
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/*
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* NOTE: Use the same window array for insertion and removal of
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* temporary windows.
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*/
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void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size)
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{
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uint32_t win_id;
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for (int i = 0; i < size; i++) {
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uint64_t base;
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uint32_t target;
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win_id = MVEBU_CCU_MAX_WINS - 1 - i;
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target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
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target >>= CCU_TARGET_ID_OFFSET;
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target &= CCU_TARGET_ID_MASK;
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base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id));
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base <<= ADDRESS_SHIFT;
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if ((win->target_id != target) || (win->base_addr != base)) {
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ERROR("%s: Trying to remove bad window-%d!\n",
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__func__, win_id);
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continue;
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}
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ccu_disable_win(ap_index, win_id);
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win++;
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}
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}
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/* Returns current DRAM window target (DRAM_0_TID, DRAM_1_TID, RAR_TID)
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* NOTE: Call only once for each AP.
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* The AP0 DRAM window is located at index 2 only at the BL31 execution start.
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* Then it relocated to index 1 for matching the rest of APs DRAM settings.
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* Calling this function after relocation will produce wrong results on AP0
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*/
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static uint32_t ccu_dram_target_get(int ap_index)
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{
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/* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2.
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* All the rest of detected APs will use window at index 1.
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* The AP0 DRAM window is moved from index 2 to 1 during
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* init_ccu() execution.
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*/
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const uint32_t win_id = (ap_index == 0) ? 2 : 1;
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uint32_t target;
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target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
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target >>= CCU_TARGET_ID_OFFSET;
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target &= CCU_TARGET_ID_MASK;
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return target;
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}
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void ccu_dram_target_set(int ap_index, uint32_t target)
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{
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/* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2.
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* All the rest of detected APs will use window at index 1.
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* The AP0 DRAM window is moved from index 2 to 1
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* during init_ccu() execution.
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*/
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const uint32_t win_id = (ap_index == 0) ? 2 : 1;
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uint32_t dram_cr;
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dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
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dram_cr &= ~(CCU_TARGET_ID_MASK << CCU_TARGET_ID_OFFSET);
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dram_cr |= (target & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET;
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mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr);
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}
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/* Setup CCU DRAM window and enable it */
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void ccu_dram_win_config(int ap_index, struct addr_map_win *win)
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{
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#if IMAGE_BLE /* BLE */
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/* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2.
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* Since the BootROM is not accessing DRAM at BLE stage,
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* the DRAM window can be temporarely disabled.
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*/
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const uint32_t win_id = (ap_index == 0) ? 2 : 1;
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#else /* end of BLE */
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/* At the ccu_init() execution stage, DRAM windows of all APs
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* are arranged at index 1.
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* The AP0 still has the old window BootROM DRAM at index 2, so
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* the window-1 can be safely disabled without breaking the DRAM access.
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*/
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const uint32_t win_id = 1;
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#endif
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ccu_disable_win(ap_index, win_id);
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/* enable write secure (and clear read secure) */
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mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id),
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CCU_WIN_ENA_WRITE_SECURE);
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ccu_win_check(win);
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ccu_enable_win(ap_index, win, win_id);
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}
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/* Save content of CCU window + GCR */
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static void ccu_save_win_range(int ap_id, int win_first,
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int win_last, uint32_t *buffer)
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{
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int win_id, idx;
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/* Save CCU */
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for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) {
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buffer[idx++] = mmio_read_32(CCU_WIN_CR_OFFSET(ap_id, win_id));
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buffer[idx++] = mmio_read_32(CCU_WIN_SCR_OFFSET(ap_id, win_id));
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buffer[idx++] = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_id, win_id));
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buffer[idx++] = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_id, win_id));
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}
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buffer[idx] = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_id));
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}
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/* Restore content of CCU window + GCR */
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static void ccu_restore_win_range(int ap_id, int win_first,
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int win_last, uint32_t *buffer)
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{
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int win_id, idx;
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/* Restore CCU */
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for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) {
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mmio_write_32(CCU_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]);
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mmio_write_32(CCU_WIN_SCR_OFFSET(ap_id, win_id), buffer[idx++]);
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mmio_write_32(CCU_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]);
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mmio_write_32(CCU_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]);
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}
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mmio_write_32(CCU_WIN_GCR_OFFSET(ap_id), buffer[idx]);
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}
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void ccu_save_win_all(int ap_id)
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{
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ccu_save_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save);
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}
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void ccu_restore_win_all(int ap_id)
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{
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ccu_restore_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save);
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}
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int init_ccu(int ap_index)
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{
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struct addr_map_win *win, *dram_win;
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uint32_t win_id, win_reg;
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uint32_t win_count, array_id;
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uint32_t dram_target;
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#if IMAGE_BLE
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/* In BootROM context CCU Window-1
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* has SRAM_TID target and should not be disabled
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*/
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const uint32_t win_start = 2;
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#else
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const uint32_t win_start = 1;
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#endif
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INFO("Initializing CCU Address decoding\n");
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/* Get the array of the windows and fill the map data */
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marvell_get_ccu_memory_map(ap_index, &win, &win_count);
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if (win_count <= 0) {
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INFO("No windows configurations found\n");
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} else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) {
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ERROR("CCU mem map array > than max available windows (%d)\n",
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MVEBU_CCU_MAX_WINS);
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win_count = MVEBU_CCU_MAX_WINS;
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}
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/* Need to set GCR to DRAM before all CCU windows are disabled for
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* securing the normal access to DRAM location, which the ATF is running
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* from. Once all CCU windows are set, which have to include the
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* dedicated DRAM window as well, the GCR can be switched to the target
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* defined by the platform configuration.
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*/
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dram_target = ccu_dram_target_get(ap_index);
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win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET;
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mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg);
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/* If the DRAM window was already configured at the BLE stage,
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* only the window target considered valid, the address range should be
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* updated according to the platform configuration.
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*/
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for (dram_win = win, array_id = 0; array_id < win_count;
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array_id++, dram_win++) {
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if (IS_DRAM_TARGET(dram_win->target_id)) {
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dram_win->target_id = dram_target;
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break;
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}
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}
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/* Disable all AP CCU windows
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* Window-0 is always bypassed since it already contains
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* data allowing the internal configuration space access
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*/
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for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) {
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ccu_disable_win(ap_index, win_id);
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/* enable write secure (and clear read secure) */
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mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id),
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CCU_WIN_ENA_WRITE_SECURE);
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}
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/* win_id is the index of the current ccu window
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* array_id is the index of the current memory map window entry
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*/
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for (win_id = win_start, array_id = 0;
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((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count));
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win_id++) {
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ccu_win_check(win);
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ccu_enable_win(ap_index, win, win_id);
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win++;
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array_id++;
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}
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/* Get & set the default target according to board topology */
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win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK)
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<< CCU_GCR_TARGET_OFFSET;
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mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg);
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#ifdef DEBUG_ADDR_MAP
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dump_ccu(ap_index);
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#endif
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INFO("Done CCU Address decoding Initializing\n");
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return 0;
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}
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