c0481acec1
This patch implements the TSP on Juno. It executes from Secure RAM. Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have been moved around. The reason is, although there was enough space overall to store the TSP in SRAM, there was no contiguous free chunk of SRAM big enough to hold it. This patch keeps the overall memory layout (i.e. keeping BL1 R/W at the bottom, BL2 at the top and BL3-1 in between) but moves the base addresses of all the bootloader images in such a way that: - memory fragmentation is reduced enough to fit BL3-2 in; - new base addresses are suitable for release builds as well as debug ones; - each image has a few extra kilobytes for future growth. BL3-1 and BL3-2 are the images which received the biggest slice of the cake since they will most probably grow the most. Change-Id: I1c5b51858700027ee283ac85d18e06863a27c72e |
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| .. | ||
| aarch64 | ||
| tsp-fvp.mk | ||
| tsp-juno.mk | ||
| tsp.ld.S | ||
| tsp.mk | ||
| tsp_interrupt.c | ||
| tsp_main.c | ||
| tsp_timer.c | ||