417 lines
13 KiB
C
417 lines
13 KiB
C
/*
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* Copyright (c) 2013, ARM Limited. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include <arch_helpers.h>
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#include <console.h>
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#include <platform.h>
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#include <psci.h>
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#include <psci_private.h>
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typedef int (*afflvl_on_handler)(unsigned long,
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aff_map_node *,
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unsigned long,
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unsigned long);
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/*******************************************************************************
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* This function checks whether a cpu which has been requested to be turned on
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* is OFF to begin with.
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******************************************************************************/
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static int cpu_on_validate_state(unsigned int state)
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{
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unsigned int psci_state;
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/* Get the raw psci state */
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psci_state = psci_get_state(state);
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if (psci_state == PSCI_STATE_ON || psci_state == PSCI_STATE_SUSPEND)
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return PSCI_E_ALREADY_ON;
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if (psci_state == PSCI_STATE_ON_PENDING)
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return PSCI_E_ON_PENDING;
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assert(psci_state == PSCI_STATE_OFF);
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Handler routine to turn a cpu on. It takes care of any generic, architectural
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* or platform specific setup required.
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* TODO: Split this code across separate handlers for each type of setup?
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******************************************************************************/
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static int psci_afflvl0_on(unsigned long target_cpu,
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aff_map_node *cpu_node,
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unsigned long ns_entrypoint,
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unsigned long context_id)
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{
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unsigned int index, plat_state;
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unsigned long psci_entrypoint;
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int rc;
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/* Sanity check to safeguard against data corruption */
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assert(cpu_node->level == MPIDR_AFFLVL0);
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/*
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* Generic management: Ensure that the cpu is off to be
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* turned on
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*/
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rc = cpu_on_validate_state(cpu_node->state);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/*
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* Arch. management: Derive the re-entry information for
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* the non-secure world from the non-secure state from
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* where this call originated.
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*/
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index = cpu_node->data;
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rc = psci_set_ns_entry_info(index, ns_entrypoint, context_id);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/* Set the secure world (EL3) re-entry point after BL1 */
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psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
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/*
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* Plat. management: Give the platform the current state
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* of the target cpu to allow it to perform the necessary
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* steps to power on.
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*/
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if (psci_plat_pm_ops->affinst_on) {
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/* Get the current physical state of this cpu */
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plat_state = psci_get_aff_phys_state(cpu_node);
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rc = psci_plat_pm_ops->affinst_on(target_cpu,
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psci_entrypoint,
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ns_entrypoint,
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cpu_node->level,
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plat_state);
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}
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return rc;
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}
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/*******************************************************************************
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* Handler routine to turn a cluster on. It takes care or any generic, arch.
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* or platform specific setup required.
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* TODO: Split this code across separate handlers for each type of setup?
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******************************************************************************/
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static int psci_afflvl1_on(unsigned long target_cpu,
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aff_map_node *cluster_node,
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unsigned long ns_entrypoint,
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unsigned long context_id)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int plat_state;
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unsigned long psci_entrypoint;
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assert(cluster_node->level == MPIDR_AFFLVL1);
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/*
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* There is no generic and arch. specific cluster
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* management required
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*/
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/*
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* Plat. management: Give the platform the current state
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* of the target cpu to allow it to perform the necessary
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* steps to power on.
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*/
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if (psci_plat_pm_ops->affinst_on) {
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plat_state = psci_get_aff_phys_state(cluster_node);
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psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
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rc = psci_plat_pm_ops->affinst_on(target_cpu,
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psci_entrypoint,
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ns_entrypoint,
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cluster_node->level,
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plat_state);
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}
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return rc;
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}
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/*******************************************************************************
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* Handler routine to turn a cluster of clusters on. It takes care or any
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* generic, arch. or platform specific setup required.
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* TODO: Split this code across separate handlers for each type of setup?
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******************************************************************************/
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static int psci_afflvl2_on(unsigned long target_cpu,
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aff_map_node *system_node,
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unsigned long ns_entrypoint,
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unsigned long context_id)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int plat_state;
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unsigned long psci_entrypoint;
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/* Cannot go beyond affinity level 2 in this psci imp. */
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assert(system_node->level == MPIDR_AFFLVL2);
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/*
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* There is no generic and arch. specific system management
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* required
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*/
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/*
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* Plat. management: Give the platform the current state
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* of the target cpu to allow it to perform the necessary
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* steps to power on.
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*/
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if (psci_plat_pm_ops->affinst_on) {
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plat_state = psci_get_aff_phys_state(system_node);
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psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
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rc = psci_plat_pm_ops->affinst_on(target_cpu,
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psci_entrypoint,
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ns_entrypoint,
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system_node->level,
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plat_state);
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}
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return rc;
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}
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/* Private data structure to make this handlers accessible through indexing */
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static const afflvl_on_handler psci_afflvl_on_handlers[] = {
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psci_afflvl0_on,
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psci_afflvl1_on,
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psci_afflvl2_on,
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};
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/*******************************************************************************
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* This function implements the core of the processing required to turn a cpu
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* on. It avoids recursion to traverse from the lowest to the highest affinity
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* level unlike the off/suspend/pon_finisher functions. It does ensure that the
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* locks are picked in the same order as the order routines to avoid deadlocks.
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* The flow is: Take all the locks until the highest affinity level, Call the
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* handlers for turning an affinity level on & finally change the state of the
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* affinity level.
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******************************************************************************/
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int psci_afflvl_on(unsigned long target_cpu,
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unsigned long entrypoint,
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unsigned long context_id,
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int current_afflvl,
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int target_afflvl)
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{
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unsigned int prev_state, next_state;
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int rc = PSCI_E_SUCCESS, level;
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aff_map_node *aff_node;
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unsigned long mpidr = read_mpidr() & MPIDR_AFFINITY_MASK;
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/*
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* This loop acquires the lock corresponding to each
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* affinity level so that by the time we hit the lowest
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* affinity level, the system topology is snapshot and
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* state management can be done safely.
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*/
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for (level = current_afflvl; level >= target_afflvl; level--) {
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aff_node = psci_get_aff_map_node(target_cpu, level);
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if (aff_node)
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bakery_lock_get(mpidr, &aff_node->lock);
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}
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/*
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* Perform generic, architecture and platform specific
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* handling
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*/
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for (level = current_afflvl; level >= target_afflvl; level--) {
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/* Grab the node for each affinity level once again */
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aff_node = psci_get_aff_map_node(target_cpu, level);
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if (aff_node) {
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/* Keep the old state and the next one handy */
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prev_state = psci_get_state(aff_node->state);
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rc = psci_afflvl_on_handlers[level](target_cpu,
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aff_node,
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entrypoint,
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context_id);
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if (rc != PSCI_E_SUCCESS) {
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psci_set_state(aff_node->state, prev_state);
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goto exit;
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}
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}
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}
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/*
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* State management: Update the states since this is the
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* target affinity level requested.
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*/
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psci_change_state(target_cpu,
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target_afflvl,
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get_max_afflvl(),
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PSCI_STATE_ON_PENDING);
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exit:
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/*
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* This loop releases the lock corresponding to each affinity level
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* in the reverse order. It also checks the final state of the cpu.
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*/
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for (level = target_afflvl; level <= current_afflvl; level++) {
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aff_node = psci_get_aff_map_node(target_cpu, level);
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if (aff_node) {
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if (level == MPIDR_AFFLVL0) {
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next_state = psci_get_state(aff_node->state);
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assert(next_state == PSCI_STATE_ON_PENDING);
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}
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bakery_lock_release(mpidr, &aff_node->lock);
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}
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}
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return rc;
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}
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/*******************************************************************************
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* The following functions finish an earlier affinity power on request. They
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* are called by the common finisher routine in psci_common.c.
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******************************************************************************/
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static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
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aff_map_node *cpu_node,
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unsigned int prev_state)
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{
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unsigned int index, plat_state, rc = PSCI_E_SUCCESS;
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assert(cpu_node->level == MPIDR_AFFLVL0);
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/*
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* Plat. management: Perform the platform specific actions
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* for this cpu e.g. enabling the gic or zeroing the mailbox
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* register. The actual state of this cpu has already been
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* changed.
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*/
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if (psci_plat_pm_ops->affinst_on_finish) {
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/* Get the previous physical state of this cpu */
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plat_state = psci_get_phys_state(prev_state);
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rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
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cpu_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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/*
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* Arch. management: Turn on mmu & restore architectural state
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*/
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write_vbar((unsigned long) runtime_exceptions);
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enable_mmu();
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/*
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* All the platform specific actions for turning this cpu
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* on have completed. Perform enough arch.initialization
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* to run in the non-secure address space.
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*/
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bl31_arch_setup();
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/*
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* Generic management: Now we just need to retrieve the
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* information that we had stashed away during the cpu_on
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* call to set this cpu on it's way. First get the index
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* for restoring the re-entry info
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*/
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index = cpu_node->data;
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rc = psci_get_ns_entry_info(index);
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/* Clean caches before re-entering normal world */
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dcsw_op_louis(DCCSW);
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return rc;
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}
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static unsigned int psci_afflvl1_on_finish(unsigned long mpidr,
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aff_map_node *cluster_node,
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unsigned int prev_state)
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{
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unsigned int rc = PSCI_E_SUCCESS;
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unsigned int plat_state;
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assert(cluster_node->level == MPIDR_AFFLVL1);
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/*
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* Plat. management: Perform the platform specific actions
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* as per the old state of the cluster e.g. enabling
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* coherency at the interconnect depends upon the state with
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* which this cluster was powered up. If anything goes wrong
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* then assert as there is no way to recover from this
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* situation.
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*/
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if (psci_plat_pm_ops->affinst_on_finish) {
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plat_state = psci_get_phys_state(prev_state);
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rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
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cluster_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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return rc;
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}
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static unsigned int psci_afflvl2_on_finish(unsigned long mpidr,
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aff_map_node *system_node,
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unsigned int prev_state)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int plat_state;
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/* Cannot go beyond this affinity level */
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assert(system_node->level == MPIDR_AFFLVL2);
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/*
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* Currently, there are no architectural actions to perform
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* at the system level.
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*/
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/*
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* Plat. management: Perform the platform specific actions
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* as per the old state of the cluster e.g. enabling
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* coherency at the interconnect depends upon the state with
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* which this cluster was powered up. If anything goes wrong
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* then assert as there is no way to recover from this
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* situation.
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*/
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if (psci_plat_pm_ops->affinst_on_finish) {
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plat_state = psci_get_phys_state(system_node->state);
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rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
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system_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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return rc;
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}
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const afflvl_power_on_finisher psci_afflvl_on_finishers[] = {
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psci_afflvl0_on_finish,
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psci_afflvl1_on_finish,
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psci_afflvl2_on_finish,
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};
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