97 lines
2.0 KiB
ArmAsm
97 lines
2.0 KiB
ArmAsm
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.global mtpmu_disable
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/* -------------------------------------------------------------
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* The functions in this file are called at entrypoint, before
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* the CPU has decided whether this is a cold or a warm boot.
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* Therefore there are no stack yet to rely on for a C function
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* call.
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* -------------------------------------------------------------
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*/
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/*
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* bool mtpmu_supported(void)
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*
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* Return a boolean indicating whether FEAT_MTPMU is supported or not.
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*
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* Trash registers: x0, x1
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*/
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func mtpmu_supported
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mrs x0, id_aa64dfr0_el1
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mov_imm x1, ID_AA64DFR0_MTPMU_MASK
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and x0, x1, x0, LSR #ID_AA64DFR0_MTPMU_SHIFT
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cmp x0, ID_AA64DFR0_MTPMU_SUPPORTED
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cset x0, eq
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ret
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endfunc mtpmu_supported
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/*
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* bool el_implemented(unsigned int el_shift)
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*
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* Return a boolean indicating if the specified EL is implemented.
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* The EL is represented as the bitmask shift on id_aa64pfr0_el1 register.
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*
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* Trash registers: x0, x1
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*/
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func el_implemented
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mrs x1, id_aa64pfr0_el1
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lsr x1, x1, x0
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cmp x1, #ID_AA64PFR0_ELX_MASK
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cset x0, eq
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ret
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endfunc el_implemented
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/*
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* void mtpmu_disable(void)
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*
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* Disable mtpmu feature if supported.
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*
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* Trash register: x0, x1, x30
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*/
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func mtpmu_disable
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mov x10, x30
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bl mtpmu_supported
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cbz x0, exit_disable
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/* FEAT_MTMPU Supported */
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mov_imm x0, ID_AA64PFR0_EL3_SHIFT
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bl el_implemented
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cbz x0, 1f
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/* EL3 implemented */
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mrs x0, mdcr_el3
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mov_imm x1, MDCR_MTPME_BIT
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bic x0, x0, x1
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msr mdcr_el3, x0
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/*
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* If EL3 is implemented, MDCR_EL2.MTPME is implemented as Res0 and
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* FEAT_MTPMU is controlled only from EL3, so no need to perform
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* any operations for EL2.
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*/
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isb
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exit_disable:
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ret x10
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1:
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/* EL3 not implemented */
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mov_imm x0, ID_AA64PFR0_EL2_SHIFT
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bl el_implemented
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cbz x0, exit_disable
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/* EL2 implemented */
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mrs x0, mdcr_el2
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mov_imm x1, MDCR_EL2_MTPME
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bic x0, x0, x1
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msr mdcr_el2, x0
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isb
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ret x10
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endfunc mtpmu_disable
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