369 lines
11 KiB
ArmAsm
369 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#include <cortex_a57.h>
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#include <cortex_a53.h>
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#include <tegra_def.h>
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/* Global functions */
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl platform_mem_init
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl tegra_secure_entrypoint
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.globl plat_reset_handler
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/* Global variables */
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.globl tegra_sec_entry_point
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.globl ns_image_entrypoint
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.globl tegra_bl31_phys_base
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/* ---------------------
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* Common CPU init code
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* ---------------------
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*/
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.macro cpu_init_common
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#if ENABLE_L2_DYNAMIC_RETENTION
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/* ---------------------------
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* Enable processor retention
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* ---------------------------
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*/
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mrs x0, L2ECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT
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bic x0, x0, #L2ECTLR_RET_CTRL_MASK
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orr x0, x0, x1
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msr L2ECTLR_EL1, x0
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isb
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#endif
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#if ENABLE_CPU_DYNAMIC_RETENTION
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mrs x0, CPUECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT
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bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK
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orr x0, x0, x1
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msr CPUECTLR_EL1, x0
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isb
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#endif
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#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
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/* -------------------------------------------------------
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* Enable L2 and CPU ECTLR RW access from non-secure world
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* -------------------------------------------------------
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*/
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mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS
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msr actlr_el3, x0
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msr actlr_el2, x0
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isb
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#endif
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/* --------------------------------
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* Enable the cycle count register
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* --------------------------------
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*/
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mrs x0, pmcr_el0
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ubfx x0, x0, #11, #5 // read PMCR.N field
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mov x1, #1
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lsl x0, x1, x0
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sub x0, x0, #1 // mask of event counters
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orr x0, x0, #0x80000000 // disable overflow intrs
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msr pmintenclr_el1, x0
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msr pmuserenr_el0, x1 // enable user mode access
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/* ----------------------------------------------------------------
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* Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count
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* register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ
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* registers from EL0.
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* ----------------------------------------------------------------
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*/
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mrs x0, cntkctl_el1
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orr x0, x0, #EL0VCTEN_BIT
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msr cntkctl_el1, x0
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.endm
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary(void);
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*
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* This function checks if this is the Primary CPU
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #TEGRA_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void);
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*
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* result: CorePos = CoreId + (ClusterId << 2)
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot. If the tegra_sec_entry_point for
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* this CPU is present, then it's a warm boot.
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*
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* -----------------------------------------------------
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*/
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func plat_get_my_entrypoint
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adr x1, tegra_sec_entry_point
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset. Right
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* now this is a stub function.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mov x0, #0
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ret
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endfunc plat_secondary_cold_boot_setup
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0 - x4
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, TEGRA_BOOT_UART_BASE
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mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ
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mov_imm x2, TEGRA_CONSOLE_BAUDRATE
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b console_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, TEGRA_BOOT_UART_BASE
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b console_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------------
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* Function to handle a platform reset and store
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* input parameters passed by BL2.
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* ---------------------------------------------------
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*/
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func plat_reset_handler
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/* -----------------------------------
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* derive and save the phys_base addr
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* -----------------------------------
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*/
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adr x17, tegra_bl31_phys_base
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ldr x18, [x17]
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cbnz x18, 1f
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adr x18, bl31_entrypoint
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str x18, [x17]
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1: cpu_init_common
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ret
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endfunc plat_reset_handler
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/* ----------------------------------------
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* Secure entrypoint function for CPU boot
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* ----------------------------------------
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*/
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.align 6
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func tegra_secure_entrypoint
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#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT
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/* -------------------------------------------------------
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* Invalidate BTB along with I$ to remove any stale
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* entries from the branch predictor array.
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* -------------------------------------------------------
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*/
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mrs x0, CPUACTLR_EL1
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orr x0, x0, #1
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msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
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dsb sy
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isb
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ic iallu /* actual invalidate */
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dsb sy
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isb
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mrs x0, CPUACTLR_EL1
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bic x0, x0, #1
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msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
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dsb sy
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isb
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.rept 7
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nop /* wait */
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.endr
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/* -----------------------------------------------
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* Extract OSLK bit and check if it is '1'. This
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* bit remains '0' for A53 on warm-resets. If '1',
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* turn off regional clock gating and request warm
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* reset.
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* -----------------------------------------------
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*/
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mrs x0, oslsr_el1
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and x0, x0, #2
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mrs x1, mpidr_el1
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bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */
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b.eq restore_oslock
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mov x0, xzr
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msr oslar_el1, x0 /* os lock stays 0 across warm reset */
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mov x3, #3
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movz x4, #0x8000, lsl #48
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msr CPUACTLR_EL1, x4 /* turn off RCG */
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isb
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msr rmr_el3, x3 /* request warm reset */
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isb
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dsb sy
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1: wfi
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b 1b
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/* --------------------------------------------------
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* These nops are here so that speculative execution
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* won't harm us before we are done with warm reset.
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* --------------------------------------------------
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*/
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.rept 65
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nop
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.endr
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/* --------------------------------------------------
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* Do not insert instructions here
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* --------------------------------------------------
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*/
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#endif
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/* --------------------------------------------------
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* Restore OS Lock bit
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* --------------------------------------------------
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*/
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restore_oslock:
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mov x0, #1
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msr oslar_el1, x0
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cpu_init_common
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* ---------------------------------------------------------------------
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*/
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mrs x1, cptr_el3
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bic w1, w1, #TCPAC_BIT
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bic w1, w1, #TTA_BIT
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bic w1, w1, #TFP_BIT
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msr cptr_el3, x1
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/* --------------------------------------------------
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* Get secure world's entry point and jump to it
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* --------------------------------------------------
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*/
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bl plat_get_my_entrypoint
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br x0
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endfunc tegra_secure_entrypoint
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.data
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.align 3
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/* --------------------------------------------------
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* CPU Secure entry point - resume from suspend
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* --------------------------------------------------
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*/
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tegra_sec_entry_point:
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.quad 0
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/* --------------------------------------------------
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* NS world's cold boot entry point
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* --------------------------------------------------
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*/
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ns_image_entrypoint:
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.quad 0
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/* --------------------------------------------------
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* BL31's physical base address
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* --------------------------------------------------
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*/
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tegra_bl31_phys_base:
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.quad 0
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