168 lines
3.9 KiB
C
168 lines
3.9 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PMIC_WRAP_INIT_H__
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#define __PMIC_WRAP_INIT_H__
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/* external API */
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int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
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int32_t pwrap_write(uint32_t adr, uint32_t wdata);
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static struct mt8173_pmic_wrap_regs *const mt8173_pwrap =
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(void *)PMIC_WRAP_BASE;
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/* timeout setting */
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enum {
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TIMEOUT_RESET = 50, /* us */
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TIMEOUT_READ = 50, /* us */
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TIMEOUT_WAIT_IDLE = 50 /* us */
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};
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/* PMIC_WRAP registers */
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struct mt8173_pmic_wrap_regs {
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uint32_t mux_sel;
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uint32_t wrap_en;
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uint32_t dio_en;
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uint32_t sidly;
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uint32_t rddmy;
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uint32_t si_ck_con;
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uint32_t cshext_write;
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uint32_t cshext_read;
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uint32_t cslext_start;
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uint32_t cslext_end;
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uint32_t staupd_prd;
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uint32_t staupd_grpen;
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uint32_t reserved[4];
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uint32_t staupd_man_trig;
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uint32_t staupd_sta;
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uint32_t wrap_sta;
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uint32_t harb_init;
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uint32_t harb_hprio;
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uint32_t hiprio_arb_en;
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uint32_t harb_sta0;
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uint32_t harb_sta1;
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uint32_t man_en;
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uint32_t man_cmd;
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uint32_t man_rdata;
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uint32_t man_vldclr;
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uint32_t wacs0_en;
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uint32_t init_done0;
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uint32_t wacs0_cmd;
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uint32_t wacs0_rdata;
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uint32_t wacs0_vldclr;
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uint32_t wacs1_en;
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uint32_t init_done1;
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uint32_t wacs1_cmd;
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uint32_t wacs1_rdata;
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uint32_t wacs1_vldclr;
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uint32_t wacs2_en;
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uint32_t init_done2;
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uint32_t wacs2_cmd;
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uint32_t wacs2_rdata;
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uint32_t wacs2_vldclr;
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uint32_t int_en;
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uint32_t int_flg_raw;
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uint32_t int_flg;
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uint32_t int_clr;
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uint32_t sig_adr;
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uint32_t sig_mode;
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uint32_t sig_value;
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uint32_t sig_errval;
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uint32_t crc_en;
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uint32_t timer_en;
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uint32_t timer_sta;
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uint32_t wdt_unit;
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uint32_t wdt_src_en;
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uint32_t wdt_flg;
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uint32_t debug_int_sel;
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uint32_t dvfs_adr0;
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uint32_t dvfs_wdata0;
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uint32_t dvfs_adr1;
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uint32_t dvfs_wdata1;
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uint32_t dvfs_adr2;
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uint32_t dvfs_wdata2;
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uint32_t dvfs_adr3;
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uint32_t dvfs_wdata3;
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uint32_t dvfs_adr4;
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uint32_t dvfs_wdata4;
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uint32_t dvfs_adr5;
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uint32_t dvfs_wdata5;
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uint32_t dvfs_adr6;
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uint32_t dvfs_wdata6;
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uint32_t dvfs_adr7;
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uint32_t dvfs_wdata7;
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uint32_t spminf_sta;
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uint32_t cipher_key_sel;
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uint32_t cipher_iv_sel;
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uint32_t cipher_en;
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uint32_t cipher_rdy;
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uint32_t cipher_mode;
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uint32_t cipher_swrst;
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uint32_t dcm_en;
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uint32_t dcm_dbc_prd;
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};
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enum {
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RDATA_WACS_RDATA_SHIFT = 0,
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RDATA_WACS_FSM_SHIFT = 16,
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RDATA_WACS_REQ_SHIFT = 19,
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RDATA_SYNC_IDLE_SHIFT,
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RDATA_INIT_DONE_SHIFT,
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RDATA_SYS_IDLE_SHIFT,
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};
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enum {
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RDATA_WACS_RDATA_MASK = 0xffff,
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RDATA_WACS_FSM_MASK = 0x7,
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RDATA_WACS_REQ_MASK = 0x1,
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RDATA_SYNC_IDLE_MASK = 0x1,
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RDATA_INIT_DONE_MASK = 0x1,
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RDATA_SYS_IDLE_MASK = 0x1,
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};
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/* WACS_FSM */
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enum {
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WACS_FSM_IDLE = 0x00,
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WACS_FSM_REQ = 0x02,
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WACS_FSM_WFDLE = 0x04,
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WACS_FSM_WFVLDCLR = 0x06,
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WACS_INIT_DONE = 0x01,
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WACS_SYNC_IDLE = 0x01,
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WACS_SYNC_BUSY = 0x00
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};
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/* error information flag */
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enum {
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E_PWR_INVALID_ARG = 1,
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E_PWR_INVALID_RW = 2,
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E_PWR_INVALID_ADDR = 3,
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E_PWR_INVALID_WDAT = 4,
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E_PWR_INVALID_OP_MANUAL = 5,
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E_PWR_NOT_IDLE_STATE = 6,
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E_PWR_NOT_INIT_DONE = 7,
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E_PWR_NOT_INIT_DONE_READ = 8,
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E_PWR_WAIT_IDLE_TIMEOUT = 9,
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E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
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E_PWR_INIT_SIDLY_FAIL = 11,
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E_PWR_RESET_TIMEOUT = 12,
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E_PWR_TIMEOUT = 13,
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E_PWR_INIT_RESET_SPI = 20,
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E_PWR_INIT_SIDLY = 21,
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E_PWR_INIT_REG_CLOCK = 22,
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E_PWR_INIT_ENABLE_PMIC = 23,
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E_PWR_INIT_DIO = 24,
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E_PWR_INIT_CIPHER = 25,
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E_PWR_INIT_WRITE_TEST = 26,
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E_PWR_INIT_ENABLE_CRC = 27,
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E_PWR_INIT_ENABLE_DEWRAP = 28,
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E_PWR_INIT_ENABLE_EVENT = 29,
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E_PWR_READ_TEST_FAIL = 30,
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E_PWR_WRITE_TEST_FAIL = 31,
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E_PWR_SWITCH_DIO = 32
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};
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#endif /* __PMIC_WRAP_INIT_H__ */
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