Varun Wadekar fbc44bd1bb Prevent RAS register access from lower ELs ... This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register accesses from EL1 or EL2 to EL3. RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438		2020-06-12 10:20:11 -07:00
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context.S	Fix exception in save/restore of EL2 registers.	2020-05-19 14:48:13 +01:00
context_mgmt.c	Prevent RAS register access from lower ELs	2020-06-12 10:20:11 -07:00
cpu_data.S	Changes necessary to support SEPARATE_NOBITS_REGION feature	2020-01-27 15:33:24 -06:00