175 lines
5.3 KiB
C
175 lines
5.3 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <cassert.h>
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#include <platform_def.h>
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#include <utils.h>
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#include <xlat_tables_v2.h>
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#include "../xlat_tables_private.h"
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#if DEBUG
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static unsigned long long xlat_arch_get_max_supported_pa(void)
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{
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/* Physical address space size for long descriptor format. */
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return (1ull << 40) - 1ull;
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}
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#endif /* DEBUG*/
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int is_mmu_enabled(void)
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{
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return (read_sctlr() & SCTLR_M_BIT) != 0;
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}
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#if PLAT_XLAT_TABLES_DYNAMIC
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void xlat_arch_tlbi_va(uintptr_t va)
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{
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/*
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* Ensure the translation table write has drained into memory before
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* invalidating the TLB entry.
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*/
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dsbishst();
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tlbimvaais(TLBI_ADDR(va));
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}
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void xlat_arch_tlbi_va_sync(void)
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{
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/* Invalidate all entries from branch predictors. */
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bpiallis();
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/*
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* A TLB maintenance instruction can complete at any time after
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* it is issued, but is only guaranteed to be complete after the
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* execution of DSB by the PE that executed the TLB maintenance
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* instruction. After the TLB invalidate instruction is
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* complete, no new memory accesses using the invalidated TLB
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* entries will be observed by any observer of the system
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* domain. See section D4.8.2 of the ARMv8 (issue k), paragraph
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* "Ordering and completion of TLB maintenance instructions".
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*/
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dsbish();
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/*
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* The effects of a completed TLB maintenance instruction are
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* only guaranteed to be visible on the PE that executed the
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* instruction after the execution of an ISB instruction by the
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* PE that executed the TLB maintenance instruction.
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*/
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isb();
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}
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#endif /* PLAT_XLAT_TABLES_DYNAMIC */
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void init_xlat_tables_arch(unsigned long long max_pa)
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{
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assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <=
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xlat_arch_get_max_supported_pa());
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}
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/*******************************************************************************
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* Function for enabling the MMU in Secure PL1, assuming that the
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* page-tables have already been created.
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******************************************************************************/
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void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table)
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{
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u_register_t mair0, ttbcr, sctlr;
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uint64_t ttbr0;
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assert(IS_IN_SECURE());
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assert((read_sctlr() & SCTLR_M_BIT) == 0);
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/* Invalidate TLBs at the current exception level */
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tlbiall();
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/* Set attributes in the right indices of the MAIR */
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mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
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ATTR_NON_CACHEABLE_INDEX);
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write_mair0(mair0);
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/*
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* Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
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*/
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if (flags & XLAT_TABLE_NC) {
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/* Inner & outer non-cacheable non-shareable. */
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ttbcr = TTBCR_EAE_BIT |
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TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
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TTBCR_RGN0_INNER_NC |
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(32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
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} else {
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/* Inner & outer WBWA & shareable. */
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ttbcr = TTBCR_EAE_BIT |
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TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
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TTBCR_RGN0_INNER_WBA |
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(32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
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}
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ttbcr |= TTBCR_EPD1_BIT;
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write_ttbcr(ttbcr);
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/* Set TTBR0 bits as well */
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ttbr0 = (uint64_t)(uintptr_t) base_table;
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write64_ttbr0(ttbr0);
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write64_ttbr1(0);
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/*
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* Ensure all translation table writes have drained
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* into memory, the TLB invalidation is complete,
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* and translation register writes are committed
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* before enabling the MMU
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*/
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dsb();
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isb();
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sctlr = read_sctlr();
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
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if (flags & DISABLE_DCACHE)
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sctlr &= ~SCTLR_C_BIT;
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else
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sctlr |= SCTLR_C_BIT;
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write_sctlr(sctlr);
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/* Ensure the MMU enable takes effect immediately */
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isb();
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}
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void enable_mmu_arch(unsigned int flags, uint64_t *base_table)
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{
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enable_mmu_internal_secure(flags, base_table);
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}
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