David Cunado 939f66d6c4 Reset EL2 and EL3 configurable controls ... This patch resets EL2 and EL3 registers that have architecturally UNKNOWN values on reset and that also provide EL2/EL3 configuration and trap controls. Specifically, the EL2 physical timer is disabled to prevent timer interrups into EL2 - CNTHP_CTL_EL2 and CNTHP_CTL for AArch64 and AArch32, respectively. Additionally, for AArch64, HSTR_EL2 is reset to avoid unexpected traps of non-secure access to certain system registers at EL1 or lower. For AArch32, the patch also reverts the reset to SDCR which was incorrectly added in a previous change. Change-Id: If00eaa23afa7dd36a922265194ccd6223187414f Signed-off-by: David Cunado <david.cunado@arm.com>		2016-12-01 16:17:39 +00:00
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context_mgmt.c	Reset EL2 and EL3 configurable controls	2016-12-01 16:17:39 +00:00
cpu_data.S	AArch32: Add support in TF libraries	2016-08-10 12:35:46 +01:00