123 lines
4.3 KiB
ArmAsm
123 lines
4.3 KiB
ArmAsm
/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <css_def.h>
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.weak plat_secondary_cold_boot_setup
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.weak platform_get_entrypoint
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.weak platform_mem_init
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.globl platform_get_core_pos
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.weak platform_is_primary_cpu
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* todo: Implement secondary CPU cold boot setup on CSS platforms */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/* -----------------------------------------------------
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* void platform_get_entrypoint (unsigned int mpid);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot.
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* On a cold boot the secondaries first wait for the
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* platform to be initialized after which they are
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* hotplugged in. The primary proceeds to perform the
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* platform initialization.
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* On a warm boot, each cpu jumps to the address in its
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* mailbox.
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*
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* TODO: Not a good idea to save lr in a temp reg
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* -----------------------------------------------------
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*/
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func platform_get_entrypoint
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mov x9, x30 // lr
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bl platform_get_core_pos
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ldr x1, =TRUSTED_MAILBOXES_BASE
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lsl x0, x0, #TRUSTED_MAILBOX_SHIFT
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ldr x0, [x1, x0]
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ret x9
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endfunc platform_get_entrypoint
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/*
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* Override the default implementation to swap the cluster order.
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* This is necessary in order to match the format of the boot
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* information passed by the SCP and read in platform_is_primary_cpu
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* below.
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*/
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func platform_get_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
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add x0, x1, x0, LSR #6
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ret
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endfunc platform_get_core_pos
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/* -----------------------------------------------------
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* void platform_mem_init(void);
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*
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* We don't need to carry out any memory initialization
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* on CSS platforms. The Secure RAM is accessible straight away.
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* -----------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* -----------------------------------------------------
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* unsigned int platform_is_primary_cpu (unsigned int mpid);
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*
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* Given the mpidr say whether this cpu is the primary
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* cpu (applicable ony after a cold boot)
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* -----------------------------------------------------
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*/
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func platform_is_primary_cpu
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mov x9, x30
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bl platform_get_core_pos
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ldr x1, =SCP_BOOT_CFG_ADDR
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ldr x1, [x1]
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ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_BIT_WIDTH
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cmp x0, x1
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cset x0, eq
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ret x9
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endfunc platform_is_primary_cpu
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