92e870843e
Cortex A78 AE erratum 2376748 is a Cat B erratum that applies to revisions <= r0p1. It is still open. The erratum states, "A PE executing a PLDW or PRFM PST instruction that lies on a mispredicted branch path might cause a second PE executing a store exclusive to the same cache line address to fail continuously." The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN is available at https://developer.arm.com/documentation/SDEN-1707912 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d |
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