232 lines
5.7 KiB
C
232 lines
5.7 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <gpc.h>
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#include <plat_imx8.h>
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#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
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#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
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#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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int imx_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int core_id;
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uint64_t base_addr = BL31_BASE;
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core_id = MPIDR_AFFLVL0_VAL(mpidr);
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/* set the secure entrypoint */
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imx_set_cpu_secure_entry(core_id, base_addr);
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/* power up the core */
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imx_set_cpu_pwr_on(core_id);
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return PSCI_E_SUCCESS;
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}
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void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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/* program the GIC per cpu dist and rdist interface */
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plat_gic_pcpu_init();
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/* enable the GICv3 cpu interface */
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plat_gic_cpuif_enable();
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}
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void imx_pwr_domain_off(const psci_power_state_t *target_state)
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{
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uint64_t mpidr = read_mpidr_el1();
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unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
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/* disable the GIC cpu interface first */
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plat_gic_cpuif_disable();
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/* config the core for power down */
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imx_set_cpu_pwr_off(core_id);
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}
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int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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/* The non-secure entrypoint should be in RAM space */
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if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET)
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return PSCI_E_INVALID_PARAMS;
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return PSCI_E_SUCCESS;
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}
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int imx_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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int pwr_type = psci_get_pstate_type(power_state);
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int state_id = psci_get_pstate_id(power_state);
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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if (pwr_type == PSTATE_TYPE_STANDBY) {
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CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
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CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
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}
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if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) {
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CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE;
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CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
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}
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return PSCI_E_SUCCESS;
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}
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void imx_cpu_standby(plat_local_state_t cpu_state)
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{
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dsb();
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write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
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isb();
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wfi();
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write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
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isb();
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}
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void imx_domain_suspend(const psci_power_state_t *target_state)
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{
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uint64_t base_addr = BL31_BASE;
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uint64_t mpidr = read_mpidr_el1();
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unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
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if (is_local_state_off(CORE_PWR_STATE(target_state))) {
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/* disable the cpu interface */
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plat_gic_cpuif_disable();
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imx_set_cpu_secure_entry(core_id, base_addr);
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imx_set_cpu_lpm(core_id, true);
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} else {
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dsb();
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write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
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isb();
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}
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if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
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imx_set_cluster_powerdown(core_id, true);
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else
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imx_set_cluster_standby(true);
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if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
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imx_set_sys_lpm(true);
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}
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}
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void imx_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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uint64_t mpidr = read_mpidr_el1();
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unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
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/* check the system level status */
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if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
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imx_set_sys_lpm(false);
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imx_clear_rbc_count();
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}
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/* check the cluster level power status */
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if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
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imx_set_cluster_powerdown(core_id, false);
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else
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imx_set_cluster_standby(false);
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/* check the core level power status */
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if (is_local_state_off(CORE_PWR_STATE(target_state))) {
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/* clear the core lpm setting */
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imx_set_cpu_lpm(core_id, false);
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/* enable the gic cpu interface */
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plat_gic_cpuif_enable();
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} else {
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write_scr_el3(read_scr_el3() & (~0x4));
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isb();
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}
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}
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void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned int i;
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for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE;
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}
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void __dead2 imx_system_reset(void)
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{
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uintptr_t wdog_base = IMX_WDOG_BASE;
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unsigned int val;
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/* WDOG_B reset */
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val = mmio_read_16(wdog_base);
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#ifdef IMX_WDOG_B_RESET
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val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_WDE |
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WDOG_WCR_WDT | WDOG_WCR_SRS;
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#else
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val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_SRS;
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#endif
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mmio_write_16(wdog_base, val);
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mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
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mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa);
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while (1)
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;
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}
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void __dead2 imx_system_off(void)
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{
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mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV |
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SNVS_LPCR_DP_EN | SNVS_LPCR_TOP);
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while (1)
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;
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}
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void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
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{
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if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
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imx_set_rbc_count();
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while (1)
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wfi();
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}
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static const plat_psci_ops_t imx_plat_psci_ops = {
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.pwr_domain_on = imx_pwr_domain_on,
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.pwr_domain_on_finish = imx_pwr_domain_on_finish,
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.pwr_domain_off = imx_pwr_domain_off,
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.validate_ns_entrypoint = imx_validate_ns_entrypoint,
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.validate_power_state = imx_validate_power_state,
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.cpu_standby = imx_cpu_standby,
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.pwr_domain_suspend = imx_domain_suspend,
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.pwr_domain_suspend_finish = imx_domain_suspend_finish,
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.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
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.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
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.system_reset = imx_system_reset,
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.system_off = imx_system_off,
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};
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/* export the platform specific psci ops */
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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imx_mailbox_init(sec_entrypoint);
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/* sec_entrypoint is used for warm reset */
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*psci_ops = &imx_plat_psci_ops;
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return 0;
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}
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