36 lines
991 B
C
36 lines
991 B
C
/*
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_SOCFPGA_DEF_H
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#define PLAT_SOCFPGA_DEF_H
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#include <platform_def.h>
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
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/* Register Mapping */
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#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
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#define SOCFPGA_MMC_REG_BASE 0xff808000
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#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
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#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
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#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
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#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300
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#endif /* PLAT_SOCFPGA_DEF_H */
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