55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
/*
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_SYSTEMMANAGER_H
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#define SOCFPGA_SYSTEMMANAGER_H
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#include "socfpga_plat_def.h"
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/* System Manager Register Map */
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#define SOCFPGA_SYSMGR_SDMMC 0x28
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#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
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#define SOCFPGA_SYSMGR_EMAC_0 0x44
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#define SOCFPGA_SYSMGR_EMAC_1 0x48
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#define SOCFPGA_SYSMGR_EMAC_2 0x4c
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#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
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#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc
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#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0
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#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224
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/* Field Masking */
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#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
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#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
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#define IDLE_DATA_LWSOC2FPGA BIT(0)
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#define IDLE_DATA_SOC2FPGA BIT(4)
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#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
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#define SYSMGR_ECC_OCRAM_MASK BIT(1)
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#define SYSMGR_ECC_DDR0_MASK BIT(16)
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#define SYSMGR_ECC_DDR1_MASK BIT(17)
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/* Macros */
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#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
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+ (SOCFPGA_SYSMGR_##_reg))
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#endif /* SOCFPGA_SYSTEMMANAGER_H */
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