186 lines
6.8 KiB
C
186 lines
6.8 KiB
C
/*
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* Copyright (c) 2013, ARM Limited. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string.h>
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#include <assert.h>
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#include <arch_helpers.h>
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#include <platform.h>
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#include <bl1.h>
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#include <console.h>
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#include <cci400.h>
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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#if defined (__GNUC__)
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extern unsigned long __FIRMWARE_ROM_START__;
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extern unsigned long __FIRMWARE_ROM_SIZE__;
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extern unsigned long __FIRMWARE_DATA_START__;
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extern unsigned long __FIRMWARE_DATA_SIZE__;
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extern unsigned long __FIRMWARE_BSS_START__;
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extern unsigned long __FIRMWARE_BSS_SIZE__;
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extern unsigned long __DATA_RAM_START__;
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extern unsigned long __DATA_RAM_SIZE__;
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extern unsigned long __BSS_RAM_START__;
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extern unsigned long __BSS_RAM_SIZE__;
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extern unsigned long __FIRMWARE_RAM_STACKS_START__;
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extern unsigned long __FIRMWARE_RAM_STACKS_SIZE__;
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extern unsigned long __FIRMWARE_RAM_PAGETABLES_START__;
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extern unsigned long __FIRMWARE_RAM_PAGETABLES_SIZE__;
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extern unsigned long __FIRMWARE_RAM_COHERENT_START__;
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extern unsigned long __FIRMWARE_RAM_COHERENT_SIZE__;
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#define BL1_COHERENT_MEM_BASE (&__FIRMWARE_RAM_COHERENT_START__)
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#define BL1_COHERENT_MEM_LIMIT \
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((unsigned long long)&__FIRMWARE_RAM_COHERENT_START__ + \
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(unsigned long long)&__FIRMWARE_RAM_COHERENT_SIZE__)
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#define BL1_FIRMWARE_RAM_GLOBALS_ZI_BASE \
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(unsigned long)(&__BSS_RAM_START__)
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#define BL1_FIRMWARE_RAM_GLOBALS_ZI_LENGTH \
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(unsigned long)(&__FIRMWARE_BSS_SIZE__)
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#define BL1_FIRMWARE_RAM_COHERENT_ZI_BASE \
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(unsigned long)(&__FIRMWARE_RAM_COHERENT_START__)
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#define BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH\
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(unsigned long)(&__FIRMWARE_RAM_COHERENT_SIZE__)
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#define BL1_NORMAL_RAM_BASE (unsigned long)(&__BSS_RAM_START__)
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#define BL1_NORMAL_RAM_LIMIT \
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((unsigned long)&__FIRMWARE_RAM_COHERENT_START__ + \
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(unsigned long)&__FIRMWARE_RAM_COHERENT_SIZE__)
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#else
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#error "Unknown compiler."
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#endif
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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static meminfo bl1_tzram_layout;
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meminfo bl1_get_sec_mem_layout(void)
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{
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return bl1_tzram_layout;
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}
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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unsigned long bl1_normal_ram_base;
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unsigned long bl1_coherent_ram_limit;
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unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE;
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/*
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* Initialize extents of the bl1 sections as per the platform
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* defined values.
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*/
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bl1_normal_ram_base = BL1_NORMAL_RAM_BASE;
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bl1_coherent_ram_limit = BL1_NORMAL_RAM_LIMIT;
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/*
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* Calculate how much ram is BL1 using & how much remains free.
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* This also includes a rudimentary mechanism to detect whether
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* the BL1 data is loaded at the top or bottom of memory.
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* TODO: add support for discontigous chunks of free ram if
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* needed. Might need dynamic memory allocation support
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* et al.
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* Also assuming that the section for coherent memory is
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* the last and for globals the first in the scatter file.
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*/
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bl1_tzram_layout.total_base = TZRAM_BASE;
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bl1_tzram_layout.total_size = TZRAM_SIZE;
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if (bl1_coherent_ram_limit == tzram_limit) {
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bl1_tzram_layout.free_base = TZRAM_BASE;
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bl1_tzram_layout.free_size = bl1_normal_ram_base - TZRAM_BASE;
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} else {
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bl1_tzram_layout.free_base = bl1_coherent_ram_limit;
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bl1_tzram_layout.free_size =
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tzram_limit - bl1_coherent_ram_limit;
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}
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/* Initialize the platform config for future decision making */
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platform_config_setup();
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}
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/*******************************************************************************
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* Function which will evaluate how much of the trusted ram has been gobbled
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* up by BL1 and return the base and size of whats available for loading BL2.
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* Its called after coherency and the MMU have been turned on.
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******************************************************************************/
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void bl1_platform_setup(void)
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{
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/*
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* This should zero out our coherent stacks as well but we don't care
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* as they are not being used right now.
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*/
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memset((void *) BL1_FIRMWARE_RAM_COHERENT_ZI_BASE, 0,
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(size_t) BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH);
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/* Enable and initialize the System level generic timer */
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mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_EN);
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/* Initialize the console */
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console_init();
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return;
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}
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/*******************************************************************************
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* Perform the very early platform specific architecture setup here. At the
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* moment this only does basic initialization. Later architectural setup
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* (bl1_arch_setup()) does not do anything platform specific.
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******************************************************************************/
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void bl1_plat_arch_setup(void)
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{
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unsigned long cci_setup;
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/*
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* Enable CCI-400 for this cluster. No need
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* for locks as no other cpu is active at the
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* moment
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*/
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup) {
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cci_enable_coherency(read_mpidr());
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}
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configure_mmu(&bl1_tzram_layout,
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TZROM_BASE, /* Read_only region start */
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TZROM_BASE + TZROM_SIZE, /* Read_only region size */
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/* Coherent region start */
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BL1_FIRMWARE_RAM_COHERENT_ZI_BASE,
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/* Coherent region size */
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BL1_FIRMWARE_RAM_COHERENT_ZI_BASE +
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BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH);
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}
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