401 lines
10 KiB
C
401 lines
10 KiB
C
/*
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* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/gpio.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <plat_private.h>
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#include <soc.h>
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struct gpio_save {
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uint32_t swporta_dr;
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uint32_t swporta_ddr;
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uint32_t inten;
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uint32_t intmask;
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uint32_t inttype_level;
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uint32_t int_polarity;
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uint32_t debounce;
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uint32_t ls_sync;
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} store_gpio[3];
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static uint32_t store_grf_gpio[(GRF_GPIO2D_HE - GRF_GPIO2A_IOMUX) / 4 + 1];
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define INTEN 0x30
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#define INTMASK 0x34
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#define INTTYPE_LEVEL 0x38
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#define INT_POLARITY 0x3c
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#define DEBOUNCE 0x48
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#define LS_SYNC 0x60
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#define EXT_PORTA 0x50
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#define PMU_GPIO_PORT0 0
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#define PMU_GPIO_PORT1 1
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#define GPIO_PORT2 2
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#define GPIO_PORT3 3
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#define GPIO_PORT4 4
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#define PMU_GRF_GPIO0A_P 0x40
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#define GRF_GPIO2A_P 0xe040
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#define GPIO_P_MASK 0x03
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#define GET_GPIO_PORT(pin) (pin / 32)
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#define GET_GPIO_NUM(pin) (pin % 32)
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#define GET_GPIO_BANK(pin) ((pin % 32) / 8)
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#define GET_GPIO_ID(pin) ((pin % 32) % 8)
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enum {
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ENC_ZDZU,
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ENC_ZUDR,
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ENC_ZUDZ,
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NUM_ENC
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};
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static const struct port_info {
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uint32_t clkgate_reg;
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uint32_t pull_base;
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uint32_t port_base;
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/*
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* Selects the pull mode encoding per bank,
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* first index for pull_type_{hw2sw,sw2hw}
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*/
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uint8_t pull_enc[4];
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uint8_t clkgate_bit;
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uint8_t max_bank;
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} port_info[] = {
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{
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.clkgate_reg = PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
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.pull_base = PMUGRF_BASE + PMUGRF_GPIO0A_P,
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.port_base = GPIO0_BASE,
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.pull_enc = {ENC_ZDZU, ENC_ZDZU},
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.clkgate_bit = PCLK_GPIO0_GATE_SHIFT,
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.max_bank = 1,
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}, {
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.clkgate_reg = PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
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.pull_base = PMUGRF_BASE + PMUGRF_GPIO1A_P,
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.port_base = GPIO1_BASE,
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.pull_enc = {ENC_ZUDR, ENC_ZUDR, ENC_ZUDR, ENC_ZUDR},
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.clkgate_bit = PCLK_GPIO1_GATE_SHIFT,
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.max_bank = 3,
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}, {
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.clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
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.pull_base = GRF_BASE + GRF_GPIO2A_P,
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.port_base = GPIO2_BASE,
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.pull_enc = {ENC_ZUDR, ENC_ZUDR, ENC_ZDZU, ENC_ZDZU},
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.clkgate_bit = PCLK_GPIO2_GATE_SHIFT,
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.max_bank = 3,
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}, {
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.clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
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.pull_base = GRF_BASE + GRF_GPIO3A_P,
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.port_base = GPIO3_BASE,
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.pull_enc = {ENC_ZUDR, ENC_ZUDR, ENC_ZUDR, ENC_ZUDR},
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.clkgate_bit = PCLK_GPIO3_GATE_SHIFT,
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.max_bank = 3,
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}, {
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.clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
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.pull_base = GRF_BASE + GRF_GPIO4A_P,
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.port_base = GPIO4_BASE,
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.pull_enc = {ENC_ZUDR, ENC_ZUDR, ENC_ZUDR, ENC_ZUDR},
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.clkgate_bit = PCLK_GPIO4_GATE_SHIFT,
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.max_bank = 3,
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}
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};
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/*
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* Mappings between TF-A constants and hardware encodings:
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* there are 3 different encoding schemes that may differ between
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* banks of the same port: the corresponding value of the pull_enc array
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* in port_info is used as the first index
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*/
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static const uint8_t pull_type_hw2sw[NUM_ENC][4] = {
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[ENC_ZDZU] = {GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_NONE, GPIO_PULL_UP},
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[ENC_ZUDR] = {GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN, GPIO_PULL_REPEATER},
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[ENC_ZUDZ] = {GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN, GPIO_PULL_NONE}
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};
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static const uint8_t pull_type_sw2hw[NUM_ENC][4] = {
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[ENC_ZDZU] = {
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[GPIO_PULL_NONE] = 0,
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[GPIO_PULL_DOWN] = 1,
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[GPIO_PULL_UP] = 3,
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[GPIO_PULL_REPEATER] = -1
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},
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[ENC_ZUDR] = {
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[GPIO_PULL_NONE] = 0,
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[GPIO_PULL_DOWN] = 2,
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[GPIO_PULL_UP] = 1,
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[GPIO_PULL_REPEATER] = 3
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},
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[ENC_ZUDZ] = {
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[GPIO_PULL_NONE] = 0,
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[GPIO_PULL_DOWN] = 2,
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[GPIO_PULL_UP] = 1,
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[GPIO_PULL_REPEATER] = -1
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}
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};
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/* Return old clock state, enables clock, in order to do GPIO access */
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static int gpio_get_clock(uint32_t gpio_number)
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{
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uint32_t port = GET_GPIO_PORT(gpio_number);
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assert(port < 5U);
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const struct port_info *info = &port_info[port];
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if ((mmio_read_32(info->clkgate_reg) & (1U << info->clkgate_bit)) == 0U) {
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return 0;
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}
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mmio_write_32(
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info->clkgate_reg,
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BITS_WITH_WMASK(0, 1, info->clkgate_bit)
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);
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return 1;
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}
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/* Restore old state of gpio clock, assuming it is running now */
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void gpio_put_clock(uint32_t gpio_number, uint32_t clock_state)
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{
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if (clock_state == 0) {
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return;
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}
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uint32_t port = GET_GPIO_PORT(gpio_number);
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const struct port_info *info = &port_info[port];
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mmio_write_32(info->clkgate_reg, BITS_WITH_WMASK(1, 1, info->clkgate_bit));
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}
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static int get_pull(int gpio)
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{
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uint32_t port = GET_GPIO_PORT(gpio);
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uint32_t bank = GET_GPIO_BANK(gpio);
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uint32_t id = GET_GPIO_ID(gpio);
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uint32_t val, clock_state;
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assert(port < 5U);
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const struct port_info *info = &port_info[port];
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assert(bank <= info->max_bank);
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clock_state = gpio_get_clock(gpio);
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val = (mmio_read_32(info->pull_base + 4 * bank) >> (id * 2)) & GPIO_P_MASK;
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gpio_put_clock(gpio, clock_state);
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return pull_type_hw2sw[info->pull_enc[bank]][val];
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}
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static void set_pull(int gpio, int pull)
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{
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uint32_t port = GET_GPIO_PORT(gpio);
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uint32_t bank = GET_GPIO_BANK(gpio);
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uint32_t id = GET_GPIO_ID(gpio);
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uint32_t clock_state;
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assert(port < 5U);
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const struct port_info *info = &port_info[port];
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assert(bank <= info->max_bank);
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uint8_t val = pull_type_sw2hw[info->pull_enc[bank]][pull];
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assert(val != (uint8_t)-1);
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clock_state = gpio_get_clock(gpio);
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mmio_write_32(
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info->pull_base + 4 * bank,
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BITS_WITH_WMASK(val, GPIO_P_MASK, id * 2)
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);
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gpio_put_clock(gpio, clock_state);
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}
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static void set_direction(int gpio, int direction)
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{
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uint32_t port = GET_GPIO_PORT(gpio);
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uint32_t num = GET_GPIO_NUM(gpio);
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uint32_t clock_state;
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assert((port < 5) && (num < 32));
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clock_state = gpio_get_clock(gpio);
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/*
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* in gpio.h
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* #define GPIO_DIR_OUT 0
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* #define GPIO_DIR_IN 1
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* but rk3399 gpio direction 1: output, 0: input
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* so need to revert direction value
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*/
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mmio_setbits_32(
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port_info[port].port_base + SWPORTA_DDR,
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((direction == 0) ? 1 : 0) << num
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);
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gpio_put_clock(gpio, clock_state);
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}
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static int get_direction(int gpio)
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{
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uint32_t port = GET_GPIO_PORT(gpio);
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uint32_t num = GET_GPIO_NUM(gpio);
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int direction, clock_state;
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assert((port < 5U) && (num < 32U));
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clock_state = gpio_get_clock(gpio);
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/*
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* in gpio.h
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* #define GPIO_DIR_OUT 0
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* #define GPIO_DIR_IN 1
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* but rk3399 gpio direction 1: output, 0: input
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* so need to revert direction value
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*/
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direction = (((mmio_read_32(
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port_info[port].port_base + SWPORTA_DDR
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) >> num) & 1U) == 0) ? 1 : 0;
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gpio_put_clock(gpio, clock_state);
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return direction;
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}
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static int get_value(int gpio)
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{
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uint32_t port = GET_GPIO_PORT(gpio);
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uint32_t num = GET_GPIO_NUM(gpio);
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int value, clock_state;
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assert((port < 5) && (num < 32));
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clock_state = gpio_get_clock(gpio);
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value = (mmio_read_32(port_info[port].port_base + EXT_PORTA) >> num) &
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0x1U;
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gpio_put_clock(gpio, clock_state);
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return value;
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}
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static void set_value(int gpio, int value)
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{
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uint32_t port = GET_GPIO_PORT(gpio);
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uint32_t num = GET_GPIO_NUM(gpio);
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uint32_t clock_state;
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assert((port < 5U) && (num < 32U));
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clock_state = gpio_get_clock(gpio);
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mmio_clrsetbits_32(
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port_info[port].port_base + SWPORTA_DR,
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1 << num,
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((value == 0) ? 0 : 1) << num
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);
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gpio_put_clock(gpio, clock_state);
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}
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void plat_rockchip_save_gpio(void)
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{
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unsigned int i;
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uint32_t cru_gate_save;
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cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31));
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/*
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* when shutdown logic, we need to save gpio2 ~ gpio4 register,
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* we need to enable gpio2 ~ gpio4 clock here, since it may be gating,
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* and we do not care gpio0 and gpio1 clock gate, since we never
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* gating them
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*/
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mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
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BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
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/*
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* since gpio0, gpio1 are pmugpio, they will keep ther value
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* when shutdown logic power rail, so only need to save gpio2 ~ gpio4
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* register value
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*/
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for (i = 2; i < 5; i++) {
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uint32_t base = port_info[i].port_base;
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store_gpio[i - 2] = (struct gpio_save) {
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.swporta_dr = mmio_read_32(base + SWPORTA_DR),
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.swporta_ddr = mmio_read_32(base + SWPORTA_DDR),
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.inten = mmio_read_32(base + INTEN),
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.intmask = mmio_read_32(base + INTMASK),
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.inttype_level = mmio_read_32(base + INTTYPE_LEVEL),
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.int_polarity = mmio_read_32(base + INT_POLARITY),
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.debounce = mmio_read_32(base + DEBOUNCE),
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.ls_sync = mmio_read_32(base + LS_SYNC),
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};
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}
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mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
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cru_gate_save | REG_SOC_WMSK);
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/*
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* gpio0, gpio1 in pmuiomux, they will keep ther value
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* when shutdown logic power rail, so only need to save gpio2 ~ gpio4
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* iomux register value
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*/
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for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++)
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store_grf_gpio[i] =
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mmio_read_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4);
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}
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void plat_rockchip_restore_gpio(void)
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{
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int i;
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uint32_t cru_gate_save;
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for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++)
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mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,
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REG_SOC_WMSK | store_grf_gpio[i]);
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cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31));
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/*
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* when shutdown logic, we need to save gpio2 ~ gpio4 register,
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* we need to enable gpio2 ~ gpio4 clock here, since it may be gating,
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* and we do not care gpio0 and gpio1 clock gate, since we never
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* gating them
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*/
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mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
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BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
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for (i = 2; i < 5; i++) {
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uint32_t base = port_info[i].port_base;
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const struct gpio_save *save = &store_gpio[i - 2];
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mmio_write_32(base + SWPORTA_DR, save->swporta_dr);
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mmio_write_32(base + SWPORTA_DDR, save->swporta_ddr);
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mmio_write_32(base + INTEN, save->inten);
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mmio_write_32(base + INTMASK, save->intmask);
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mmio_write_32(base + INTTYPE_LEVEL, save->inttype_level),
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mmio_write_32(base + INT_POLARITY, save->int_polarity);
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mmio_write_32(base + DEBOUNCE, save->debounce);
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mmio_write_32(base + LS_SYNC, save->ls_sync);
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}
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mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
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cru_gate_save | REG_SOC_WMSK);
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}
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const gpio_ops_t rk3399_gpio_ops = {
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.get_direction = get_direction,
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.set_direction = set_direction,
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.get_value = get_value,
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.set_value = set_value,
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.set_pull = set_pull,
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.get_pull = get_pull,
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};
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void plat_rockchip_gpio_init(void)
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{
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gpio_init(&rk3399_gpio_ops);
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}
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