25 lines
496 B
C
25 lines
496 B
C
/*
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* Copyright (c) 2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_EMAC_H
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#define SOCFPGA_EMAC_H
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/* EMAC PHY Mode */
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#define PHY_INTERFACE_MODE_GMII_MII 0
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#define PHY_INTERFACE_MODE_RGMII 1
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#define PHY_INTERFACE_MODE_RMII 2
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#define PHY_INTERFACE_MODE_RESET 3
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/* Mask Definitions */
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#define PHY_INTF_SEL_MSK 0x3
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#define FPGAINTF_EN_3_EMAC_MSK(x) (1 << (x * 8))
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void socfpga_emac_init(void);
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#endif /* SOCFPGA_EMAC_H */
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