251 lines
7.0 KiB
C
251 lines
7.0 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <debug.h>
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#include <desc_image_load.h>
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#include <errno.h>
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#include <generic_delay_timer.h>
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#include <hi3660.h>
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#include <mmio.h>
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#ifdef SPD_opteed
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#include <optee_utils.h>
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#endif
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#include <platform_def.h>
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#include <string.h>
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#include <ufs.h>
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#include "hikey960_def.h"
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#include "hikey960_private.h"
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/*
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* The next 2 constants identify the extents of the code & RO data region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
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*/
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#define BL2_RO_BASE (unsigned long)(&__RO_START__)
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#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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extern int load_lpm3(void);
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/*******************************************************************************
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* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
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* Return 0 on success, -1 otherwise.
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******************************************************************************/
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int plat_hikey960_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
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{
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int i;
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int *buf;
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assert(scp_bl2_image_info->image_size < SCP_BL2_SIZE);
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INFO("BL2: Initiating SCP_BL2 transfer to SCP\n");
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INFO("BL2: SCP_BL2: 0x%lx@0x%x\n",
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scp_bl2_image_info->image_base,
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scp_bl2_image_info->image_size);
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buf = (int *)scp_bl2_image_info->image_base;
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INFO("BL2: SCP_BL2 HEAD:\n");
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for (i = 0; i < 64; i += 4)
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INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n",
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buf[i], buf[i+1], buf[i+2], buf[i+3]);
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buf = (int *)(scp_bl2_image_info->image_base +
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scp_bl2_image_info->image_size - 256);
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INFO("BL2: SCP_BL2 TAIL:\n");
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for (i = 0; i < 64; i += 4)
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INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n",
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buf[i], buf[i+1], buf[i+2], buf[i+3]);
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INFO("BL2: SCP_BL2 transferred to SCP\n");
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load_lpm3();
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(void)buf;
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return 0;
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}
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void hikey960_init_ufs(void)
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{
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ufs_params_t ufs_params;
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memset(&ufs_params, 0, sizeof(ufs_params_t));
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ufs_params.reg_base = UFS_REG_BASE;
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ufs_params.desc_base = HIKEY960_UFS_DESC_BASE;
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ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE;
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ufs_params.flags = UFS_FLAGS_SKIPINIT;
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ufs_init(NULL, &ufs_params);
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}
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/*******************************************************************************
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* Gets SPSR for BL32 entry
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******************************************************************************/
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uint32_t hikey960_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL3-2 image.
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*/
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return 0;
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}
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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#ifndef AARCH32
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uint32_t hikey960_get_spsr_for_bl33_entry(void)
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{
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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#else
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uint32_t hikey960_get_spsr_for_bl33_entry(void)
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{
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unsigned int hyp_status, mode, spsr;
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hyp_status = GET_VIRT_EXT(read_id_pfr1());
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mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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#endif /* AARCH32 */
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int hikey960_bl2_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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#ifdef SPD_opteed
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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#endif
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assert(bl_mem_params);
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switch (image_id) {
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#ifdef AARCH64
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case BL32_IMAGE_ID:
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#ifdef SPD_opteed
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0) {
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WARN("OPTEE header parse error.\n");
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}
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#endif
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bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl32_entry();
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break;
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#endif
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case BL33_IMAGE_ID:
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl33_entry();
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break;
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#ifdef SCP_BL2_BASE
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case SCP_BL2_IMAGE_ID:
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/* The subsequent handling of SCP_BL2 is platform specific */
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err = plat_hikey960_bl2_handle_scp_bl2(&bl_mem_params->image_info);
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if (err) {
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WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
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}
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break;
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#endif
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}
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return err;
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}
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/*******************************************************************************
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* This function can be used by the platforms to update/use image
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* information for given `image_id`.
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******************************************************************************/
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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return hikey960_bl2_handle_post_image_load(image_id);
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}
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void bl2_early_platform_setup(meminfo_t *mem_layout)
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{
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unsigned int id, uart_base;
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generic_delay_timer_init();
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hikey960_read_boardid(&id);
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if (id == 5300)
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uart_base = PL011_UART5_BASE;
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else
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uart_base = PL011_UART6_BASE;
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/* Initialize the console to provide early debug support */
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console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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}
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void bl2_plat_arch_setup(void)
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{
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hikey960_init_mmu_el1(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL2_RO_BASE,
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BL2_RO_LIMIT,
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BL2_COHERENT_RAM_BASE,
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BL2_COHERENT_RAM_LIMIT);
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}
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void bl2_platform_setup(void)
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{
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/* disable WDT0 */
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if (mmio_read_32(WDT0_REG_BASE + WDT_LOCK_OFFSET) == WDT_LOCKED) {
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mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, WDT_UNLOCK);
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mmio_write_32(WDT0_REG_BASE + WDT_CONTROL_OFFSET, 0);
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mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, 0);
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}
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}
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