288 lines
7.8 KiB
C
288 lines
7.8 KiB
C
/*
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* Copyright (c) 2016-2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <dmu.h>
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#define IHOST0_CONFIG_ROOT 0x66000000
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#define IHOST1_CONFIG_ROOT 0x66002000
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#define IHOST2_CONFIG_ROOT 0x66004000
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#define IHOST3_CONFIG_ROOT 0x66006000
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#define A72_CRM_PLL_PWR_ON 0x00000070
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#define A72_CRM_PLL_PWR_ON__PLL0_RESETB_R 4
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#define A72_CRM_PLL_PWR_ON__PLL0_POST_RESETB_R 5
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#define A72_CRM_PLL_CHNL_BYPS_EN 0x000000ac
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#define A72_CRM_PLL_CHNL_BYPS_EN__PLL_0_CHNL_0_BYPS_EN_R 0
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#define A72_CRM_PLL_CHNL_BYPS_EN_DATAMASK 0x0000ec1f
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#define A72_CRM_PLL_CMD 0x00000080
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#define A72_CRM_PLL_CMD__UPDATE_PLL0_FREQUENCY_VCO_R 0
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#define A72_CRM_PLL_CMD__UPDATE_PLL0_FREQUENCY_POST_R 1
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#define A72_CRM_PLL_STATUS 0x00000084
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#define A72_CRM_PLL_STATUS__PLL0_LOCK_R 9
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#define A72_CRM_PLL0_CTRL1 0x00000100
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#define A72_CRM_PLL0_CTRL2 0x00000104
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#define A72_CRM_PLL0_CTRL3 0x00000108
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#define A72_CRM_PLL0_CTRL3__PLL0_PDIV_R 12
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#define A72_CRM_PLL0_CTRL4 0x0000010c
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#define A72_CRM_PLL0_CTRL4__PLL0_KP_R 0
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#define A72_CRM_PLL0_CTRL4__PLL0_KI_R 4
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#define A72_CRM_PLL0_CTRL4__PLL0_KA_R 7
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#define A72_CRM_PLL0_CTRL4__PLL0_FREFEFF_INFO_R 10
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#define PLL_MODE_VCO 0x0
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#define PLL_MODE_BYPASS 0x1
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#define PLL_RESET_TYPE_PLL 0x1
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#define PLL_RESET_TYPE_POST 0x2
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#define PLL_VCO 0x1
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#define PLL_POSTDIV 0x2
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#define ARM_FREQ_3G PLL_FREQ_FULL
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#define ARM_FREQ_1P5G PLL_FREQ_HALF
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#define ARM_FREQ_750M PLL_FREQ_QRTR
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static unsigned int ARMCOE_crm_getBaseAddress(unsigned int cluster_num)
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{
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unsigned int ihostx_config_root;
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switch (cluster_num) {
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case 0:
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default:
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ihostx_config_root = IHOST0_CONFIG_ROOT;
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break;
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case 1:
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ihostx_config_root = IHOST1_CONFIG_ROOT;
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break;
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case 2:
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ihostx_config_root = IHOST2_CONFIG_ROOT;
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break;
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case 3:
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ihostx_config_root = IHOST3_CONFIG_ROOT;
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break;
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}
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return ihostx_config_root;
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}
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static void ARMCOE_crm_pllAssertReset(unsigned int cluster_num,
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unsigned int reset_type)
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{
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unsigned long ihostx_config_root;
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unsigned int pll_rst_ctrl;
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ihostx_config_root = ARMCOE_crm_getBaseAddress(cluster_num);
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pll_rst_ctrl = mmio_read_32(ihostx_config_root + A72_CRM_PLL_PWR_ON);
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// PLL reset
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if (reset_type & PLL_RESET_TYPE_PLL) {
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pll_rst_ctrl &= ~(0x1<<A72_CRM_PLL_PWR_ON__PLL0_RESETB_R);
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}
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// post-div channel reset
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if (reset_type & PLL_RESET_TYPE_POST) {
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pll_rst_ctrl &= ~(0x1<<A72_CRM_PLL_PWR_ON__PLL0_POST_RESETB_R);
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}
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mmio_write_32(ihostx_config_root + A72_CRM_PLL_PWR_ON, pll_rst_ctrl);
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}
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static void ARMCOE_crm_pllSetMode(unsigned int cluster_num, unsigned int mode)
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{
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unsigned long ihostx_config_root;
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unsigned int pll_byp_ctrl;
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ihostx_config_root = ARMCOE_crm_getBaseAddress(cluster_num);
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pll_byp_ctrl = mmio_read_32(ihostx_config_root +
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A72_CRM_PLL_CHNL_BYPS_EN);
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if (mode == PLL_MODE_VCO) {
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// use PLL DCO output
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pll_byp_ctrl &=
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~BIT(A72_CRM_PLL_CHNL_BYPS_EN__PLL_0_CHNL_0_BYPS_EN_R);
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} else {
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// use PLL bypass sources
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pll_byp_ctrl |=
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BIT(A72_CRM_PLL_CHNL_BYPS_EN__PLL_0_CHNL_0_BYPS_EN_R);
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}
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mmio_write_32(ihostx_config_root + A72_CRM_PLL_CHNL_BYPS_EN,
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pll_byp_ctrl);
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}
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static void ARMCOE_crm_pllFreqSet(unsigned int cluster_num,
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unsigned int ihost_pll_freq_sel,
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unsigned int pdiv)
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{
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unsigned int ndiv_int;
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unsigned int ndiv_frac_low, ndiv_frac_high;
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unsigned long ihostx_config_root;
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ndiv_frac_low = 0x0;
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ndiv_frac_high = 0x0;
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if (ihost_pll_freq_sel == ARM_FREQ_3G) {
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ndiv_int = 0x78;
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} else if (ihost_pll_freq_sel == ARM_FREQ_1P5G) {
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ndiv_int = 0x3c;
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} else if (ihost_pll_freq_sel == ARM_FREQ_750M) {
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ndiv_int = 0x1e;
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} else {
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return;
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}
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ndiv_int &= 0x3FF; // low 10 bits
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ndiv_frac_low &= 0x3FF;
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ndiv_frac_high &= 0x3FF;
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ihostx_config_root = ARMCOE_crm_getBaseAddress(cluster_num);
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mmio_write_32(ihostx_config_root+A72_CRM_PLL0_CTRL1, ndiv_frac_low);
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mmio_write_32(ihostx_config_root+A72_CRM_PLL0_CTRL2, ndiv_frac_high);
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mmio_write_32(ihostx_config_root+A72_CRM_PLL0_CTRL3,
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ndiv_int |
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((pdiv << A72_CRM_PLL0_CTRL3__PLL0_PDIV_R & 0xF000)));
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mmio_write_32(ihostx_config_root + A72_CRM_PLL0_CTRL4,
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/* From Section 10 of PLL spec */
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(3 << A72_CRM_PLL0_CTRL4__PLL0_KP_R) |
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/* From Section 10 of PLL spec */
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(2 << A72_CRM_PLL0_CTRL4__PLL0_KI_R) |
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/* Normal mode (i.e. not fast-locking) */
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(0 << A72_CRM_PLL0_CTRL4__PLL0_KA_R) |
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/* 50 MHz */
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(50 << A72_CRM_PLL0_CTRL4__PLL0_FREFEFF_INFO_R));
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}
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static void ARMCOE_crm_pllDeassertReset(unsigned int cluster_num,
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unsigned int reset_type)
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{
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unsigned long ihostx_config_root;
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unsigned int pll_rst_ctrl;
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ihostx_config_root = ARMCOE_crm_getBaseAddress(cluster_num);
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pll_rst_ctrl = mmio_read_32(ihostx_config_root + A72_CRM_PLL_PWR_ON);
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// PLL reset
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if (reset_type & PLL_RESET_TYPE_PLL) {
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pll_rst_ctrl |= (0x1 << A72_CRM_PLL_PWR_ON__PLL0_RESETB_R);
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}
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// post-div channel reset
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if (reset_type & PLL_RESET_TYPE_POST) {
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pll_rst_ctrl |= (0x1 << A72_CRM_PLL_PWR_ON__PLL0_POST_RESETB_R);
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}
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mmio_write_32(ihostx_config_root + A72_CRM_PLL_PWR_ON, pll_rst_ctrl);
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}
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static void ARMCOE_crm_pllUpdate(unsigned int cluster_num, unsigned int type)
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{
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unsigned long ihostx_config_root;
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unsigned int pll_cmd;
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ihostx_config_root = ARMCOE_crm_getBaseAddress(cluster_num);
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pll_cmd = mmio_read_32(ihostx_config_root + A72_CRM_PLL_CMD);
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// VCO update
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if (type & PLL_VCO) {
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pll_cmd |= BIT(A72_CRM_PLL_CMD__UPDATE_PLL0_FREQUENCY_VCO_R);
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}
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// post-div channel update
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if (type & PLL_POSTDIV) {
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pll_cmd |= BIT(A72_CRM_PLL_CMD__UPDATE_PLL0_FREQUENCY_POST_R);
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}
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mmio_write_32(ihostx_config_root+A72_CRM_PLL_CMD, pll_cmd);
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}
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static void insert_delay(unsigned int delay)
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{
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volatile unsigned int index;
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for (index = 0; index < delay; index++)
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;
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}
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/*
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* Returns 1 if PLL locked within certain interval
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*/
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static unsigned int ARMCOE_crm_pllIsLocked(unsigned int cluster_num)
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{
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unsigned long ihostx_config_root;
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unsigned int lock_status;
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unsigned int i;
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ihostx_config_root = ARMCOE_crm_getBaseAddress(cluster_num);
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/* wait a while for pll to lock before returning from this function */
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for (i = 0; i < 1500; i++) {
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insert_delay(256);
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lock_status = mmio_read_32(ihostx_config_root +
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A72_CRM_PLL_STATUS);
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if (lock_status & BIT(A72_CRM_PLL_STATUS__PLL0_LOCK_R))
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return 1;
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}
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ERROR("PLL of Cluster #%u failed to lock\n", cluster_num);
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return 0;
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}
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/*
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* ihost PLL Variable Frequency Configuration
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*
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* Frequency Limit {VCO,ARM} (GHz):
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* 0 - no limit,
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* 1 - {3.0,1.5},
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* 2 - {4.0,2.0},
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* 3 - {5.0,2.5}
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*/
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uint32_t bcm_set_ihost_pll_freq(uint32_t cluster_num, int ihost_pll_freq_sel)
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{
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NOTICE("cluster: %u, freq_sel:0x%x\n", cluster_num, ihost_pll_freq_sel);
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//bypass PLL
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ARMCOE_crm_pllSetMode(cluster_num, PLL_MODE_BYPASS);
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//assert reset
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ARMCOE_crm_pllAssertReset(cluster_num,
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PLL_RESET_TYPE_PLL | PLL_RESET_TYPE_POST);
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//set ndiv_int for different freq
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ARMCOE_crm_pllFreqSet(cluster_num, ihost_pll_freq_sel, 0x1);
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//de-assert reset
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ARMCOE_crm_pllDeassertReset(cluster_num, PLL_RESET_TYPE_PLL);
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ARMCOE_crm_pllUpdate(cluster_num, PLL_VCO);
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//waiting for PLL lock
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ARMCOE_crm_pllIsLocked(cluster_num);
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ARMCOE_crm_pllDeassertReset(cluster_num, PLL_RESET_TYPE_POST);
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//disable bypass PLL
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ARMCOE_crm_pllSetMode(cluster_num, PLL_MODE_VCO);
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return 0;
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}
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uint32_t bcm_get_ihost_pll_freq(uint32_t cluster_num)
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{
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unsigned long ihostx_config_root;
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uint32_t ndiv_int;
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uint32_t ihost_pll_freq_sel;
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ihostx_config_root = ARMCOE_crm_getBaseAddress(cluster_num);
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ndiv_int = mmio_read_32(ihostx_config_root+A72_CRM_PLL0_CTRL3) & 0x3FF;
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if (ndiv_int == 0x78) {
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ihost_pll_freq_sel = ARM_FREQ_3G;
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} else if (ndiv_int == 0x3c) {
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ihost_pll_freq_sel = ARM_FREQ_1P5G;
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} else if (ndiv_int == 0x1e) {
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ihost_pll_freq_sel = ARM_FREQ_750M;
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} else {
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/* return unlimit otherwise*/
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ihost_pll_freq_sel = 0;
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}
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return ihost_pll_freq_sel;
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}
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