271 lines
7.7 KiB
C
271 lines
7.7 KiB
C
/*
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* Copyright (c) 2015-2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <plat/common/common_def.h>
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#include <brcm_def.h>
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#include <cmn_plat_def.h>
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#include "sr_def.h"
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/*
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* Most platform porting definitions provided by included headers
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*/
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#define PLAT_BRCM_SCP_TZC_DRAM1_SIZE ULL(0x0)
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/*
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* Required by standard platform porting definitions
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*/
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#define PLATFORM_CLUSTER0_CORE_COUNT 2
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#define PLATFORM_CLUSTER1_CORE_COUNT 2
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#define PLATFORM_CLUSTER2_CORE_COUNT 2
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#define PLATFORM_CLUSTER3_CORE_COUNT 2
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#define BRCM_SYSTEM_COUNT 1
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#define BRCM_CLUSTER_COUNT 4
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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PLATFORM_CLUSTER1_CORE_COUNT+ \
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PLATFORM_CLUSTER2_CORE_COUNT+ \
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PLATFORM_CLUSTER3_CORE_COUNT)
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#define PLAT_NUM_PWR_DOMAINS (BRCM_SYSTEM_COUNT + \
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BRCM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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/* TBD-STINGRAY */
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#define CACHE_WRITEBACK_SHIFT 6
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/* TBD-STINGRAY */
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#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
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#define BL1_PLATFORM_STACK_SIZE 0x3300
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#define BL2_PLATFORM_STACK_SIZE 0xc000
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#define BL11_PLATFORM_STACK_SIZE 0x2b00
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#define DEFAULT_PLATFORM_STACK_SIZE 0x400
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#if IMAGE_BL1
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# define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE
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#else
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#if IMAGE_BL2
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#ifdef USE_BL1_RW
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# define PLATFORM_STACK_SIZE BL2_PLATFORM_STACK_SIZE
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#else
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# define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE
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#endif
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#else
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#if IMAGE_BL11
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# define PLATFORM_STACK_SIZE BL11_PLATFORM_STACK_SIZE
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#else
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# define PLATFORM_STACK_SIZE DEFAULT_PLATFORM_STACK_SIZE
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#endif
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#endif
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#endif
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#define PLAT_BRCM_TRUSTED_SRAM_BASE 0x66D00000
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#define PLAT_BRCM_TRUSTED_SRAM_SIZE 0x00040000
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#ifdef RUN_BL1_FROM_QSPI /* BL1 XIP from QSPI */
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# define PLAT_BRCM_TRUSTED_ROM_BASE QSPI_BASE_ADDR
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#elif RUN_BL1_FROM_NAND /* BL1 XIP from NAND */
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# define PLAT_BRCM_TRUSTED_ROM_BASE NAND_BASE_ADDR
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#else /* BL1 executed in ROM */
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# define PLAT_BRCM_TRUSTED_ROM_BASE ROM_BASE_ADDR
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#endif
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#define PLAT_BRCM_TRUSTED_ROM_SIZE 0x00040000
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/*******************************************************************************
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* BL1 specific defines.
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******************************************************************************/
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#define BL1_RO_BASE PLAT_BRCM_TRUSTED_ROM_BASE
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#define BL1_RO_LIMIT (PLAT_BRCM_TRUSTED_ROM_BASE \
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+ PLAT_BRCM_TRUSTED_ROM_SIZE)
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/*
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* Put BL1 RW at the beginning of the Trusted SRAM.
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*/
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#define BL1_RW_BASE (BRCM_BL_RAM_BASE)
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#define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000)
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#define BL11_RW_BASE BL1_RW_LIMIT
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#define BL11_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \
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PLAT_BRCM_TRUSTED_SRAM_SIZE)
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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#if RUN_BL2_FROM_QSPI /* BL2 XIP from QSPI */
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#define BL2_BASE QSPI_BASE_ADDR
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#define BL2_LIMIT (BL2_BASE + 0x40000)
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#define BL2_RW_BASE BL1_RW_LIMIT
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#define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \
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PLAT_BRCM_TRUSTED_SRAM_SIZE)
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#elif RUN_BL2_FROM_NAND /* BL2 XIP from NAND */
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#define BL2_BASE NAND_BASE_ADDR
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#define BL2_LIMIT (BL2_BASE + 0x40000)
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#define BL2_RW_BASE BL1_RW_LIMIT
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#define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \
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PLAT_BRCM_TRUSTED_SRAM_SIZE)
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#else
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#define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE)
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#define BL2_LIMIT (BRCM_BL_RAM_BASE + BRCM_BL_RAM_SIZE)
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#endif
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/*
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* BL1 persistent area in internal SRAM
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* This area will increase as more features gets into BL1
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*/
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#define BL1_PERSISTENT_DATA_SIZE 0x2000
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/* To reduce BL2 runtime footprint, we can re-use some BL1_RW area */
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#define BL1_RW_RECLAIM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \
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BL1_PERSISTENT_DATA_SIZE)
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/*******************************************************************************
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* BL3-1 specific defines.
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******************************************************************************/
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/* Max Size of BL31 (in DRAM) */
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#define PLAT_BRCM_MAX_BL31_SIZE 0x30000
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#ifdef USE_DDR
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#define BL31_BASE BRCM_AP_TZC_DRAM1_BASE
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#define BL31_LIMIT (BRCM_AP_TZC_DRAM1_BASE + \
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PLAT_BRCM_MAX_BL31_SIZE)
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#else
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/* Put BL3-1 at the end of external on-board SRAM connected as NOR flash */
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#define BL31_BASE (NOR_BASE_ADDR + NOR_SIZE - \
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PLAT_BRCM_MAX_BL31_SIZE)
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#define BL31_LIMIT (NOR_BASE_ADDR + NOR_SIZE)
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#endif
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#define SECURE_DDR_END_ADDRESS BL31_LIMIT
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#ifdef NEED_SCP_BL2
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#define SCP_BL2_BASE BL31_BASE
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#define PLAT_MAX_SCP_BL2_SIZE 0x9000
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#define PLAT_SCP_COM_SHARED_MEM_BASE (CRMU_SHARED_SRAM_BASE)
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/* dummy defined */
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#define PLAT_BRCM_MHU_BASE 0x0
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#endif
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#define SECONDARY_CPU_SPIN_BASE_ADDR BRCM_SHARED_RAM_BASE
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/* Generic system timer counter frequency */
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#ifndef SYSCNT_FREQ
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#define SYSCNT_FREQ (125 * 1000 * 1000)
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#endif
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/*
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* Enable the BL32 definitions, only when optee os is selected as secure
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* payload (BL32).
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*/
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#ifdef SPD_opteed
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/*
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* Reserved Memory Map : SHMEM & TZDRAM.
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*
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* +--------+----------+ 0x8D000000
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* | SHMEM (NS) | 16MB
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* +-------------------+ 0x8E000000
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* | | TEE_RAM(S)| 4MB
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* + TZDRAM +----------+ 0x8E400000
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* | | TA_RAM(S) | 12MB
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* +-------------------+ 0x8F000000
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* | BL31 Binary (S) | 192KB
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* +-------------------+ 0x8F030000
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*/
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#define BL32_VA_SIZE (4 * 1024 * 1024)
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#define BL32_BASE (0x8E000000)
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#define BL32_LIMIT (BL32_BASE + BL32_VA_SIZE)
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#define TSP_SEC_MEM_BASE BL32_BASE
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#define TSP_SEC_MEM_SIZE BL32_VA_SIZE
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#endif
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#ifdef SPD_opteed
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#define SECURE_DDR_BASE_ADDRESS BL32_BASE
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#else
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#define SECURE_DDR_BASE_ADDRESS BL31_BASE
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#endif
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define MAX_XLAT_TABLES 7
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#define PLAT_BRCM_MMAP_ENTRIES 10
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#define MAX_MMAP_REGIONS (PLAT_BRCM_MMAP_ENTRIES + \
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BRCM_BL_REGIONS)
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#ifdef USE_DDR
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#ifdef BL33_OVERRIDE_LOAD_ADDR
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#define PLAT_BRCM_NS_IMAGE_OFFSET BL33_OVERRIDE_LOAD_ADDR
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#else
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/*
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* BL3-3 image starting offset.
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* Putting start of DRAM as of now.
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*/
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#define PLAT_BRCM_NS_IMAGE_OFFSET 0x80000000
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#endif /* BL33_OVERRIDE_LOAD_ADDR */
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#else
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/*
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* BL3-3 image starting offset.
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* Putting start of external on-board SRAM as of now.
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*/
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#define PLAT_BRCM_NS_IMAGE_OFFSET NOR_BASE_ADDR
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#endif /* USE_DDR */
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/******************************************************************************
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* Required platform porting definitions common to all BRCM platforms
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*****************************************************************************/
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#define MAX_IO_DEVICES 5
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#define MAX_IO_HANDLES 6
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#define PRIMARY_CPU 0
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/* GIC Parameter */
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#define PLAT_BRCM_GICD_BASE GIC500_BASE
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#define PLAT_BRCM_GICR_BASE (GIC500_BASE + 0x200000)
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/* Define secure interrupt as per Group here */
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#define PLAT_BRCM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(BRCM_IRQ_SEC_SPI_0, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE)
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#define PLAT_BRCM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
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GIC_INTR_CFG_EDGE), \
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/*
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*CCN 502 related constants.
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*/
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#define PLAT_BRCM_CLUSTER_COUNT 4 /* Number of RN-F Masters */
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#define PLAT_BRCM_CLUSTER_TO_CCN_ID_MAP CLUSTER0_NODE_ID, CLUSTER1_NODE_ID, CLUSTER2_NODE_ID, CLUSTER3_NODE_ID
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#define CCN_SIZE 0x1000000
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#define CLUSTER0_NODE_ID 1
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#define CLUSTER1_NODE_ID 7
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#define CLUSTER2_NODE_ID 9
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#define CLUSTER3_NODE_ID 15
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#endif
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