356 lines
13 KiB
C
356 lines
13 KiB
C
/*
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* Copyright (c) 2016 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <dmu.h>
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#include <ihost_pm.h>
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#include <platform_def.h>
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#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST1 2
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#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST2 1
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#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST3 0
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#define CDRU_MISC_RESET_CONTROL__CDRU_IH1_RESET 9
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#define CDRU_MISC_RESET_CONTROL__CDRU_IH2_RESET 8
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#define CDRU_MISC_RESET_CONTROL__CDRU_IH3_RESET 7
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#define A72_CRM_SOFTRESETN_0 0x480
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#define A72_CRM_SOFTRESETN_1 0x484
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#define A72_CRM_DOMAIN_4_CONTROL 0x810
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#define A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_DFT 3
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#define A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_MEM 6
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#define A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_I_O 0
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#define A72_CRM_SUBSYSTEM_MEMORY_CONTROL_3 0xB4C
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#define MEMORY_PDA_HI_SHIFT 0x0
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#define A72_CRM_PLL_PWR_ON 0x70
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#define A72_CRM_PLL_PWR_ON__PLL0_ISO_PLLOUT 4
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#define A72_CRM_PLL_PWR_ON__PLL0_PWRON_LDO 1
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#define A72_CRM_PLL_PWR_ON__PLL0_PWRON_PLL 0
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#define A72_CRM_SUBSYSTEM_MEMORY_CONTROL_2 0xB48
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#define A72_CRM_PLL_INTERRUPT_STATUS 0x8c
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#define A72_CRM_PLL_INTERRUPT_STATUS__PLL0_LOCK_LOST_STATUS 8
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#define A72_CRM_PLL_INTERRUPT_STATUS__PLL0_LOCK_STATUS 9
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#define A72_CRM_INTERRUPT_ENABLE 0x4
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#define A72_CRM_INTERRUPT_ENABLE__PLL0_INT_ENABLE 4
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#define A72_CRM_PLL_INTERRUPT_ENABLE 0x88
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#define A72_CRM_PLL_INTERRUPT_ENABLE__PLL0_LOCK_STATUS_INT_ENB 9
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#define A72_CRM_PLL_INTERRUPT_ENABLE__PLL0_LOCK_LOST_STATUS_INT_ENB 8
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#define A72_CRM_PLL0_CFG0_CTRL 0x120
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#define A72_CRM_PLL0_CFG1_CTRL 0x124
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#define A72_CRM_PLL0_CFG2_CTRL 0x128
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#define A72_CRM_PLL0_CFG3_CTRL 0x12C
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#define A72_CRM_CORE_CONFIG_DBGCTRL__DBGROMADDRV 0
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#define A72_CRM_CORE_CONFIG_DBGCTRL 0xD50
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#define A72_CRM_CORE_CONFIG_DBGROM_LO 0xD54
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#define A72_CRM_CORE_CONFIG_DBGROM_HI 0xD58
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#define A72_CRM_SUBSYSTEM_CONFIG_1__DBGL1RSTDISABLE 2
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#define A72_CRM_SOFTRESETN_0__CRYSTAL26_SOFTRESETN 0
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#define A72_CRM_SOFTRESETN_0__CRM_PLL0_SOFTRESETN 1
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#define A72_CRM_AXI_CLK_DESC 0x304
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#define A72_CRM_ACP_CLK_DESC 0x308
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#define A72_CRM_ATB_CLK_DESC 0x30C
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#define A72_CRM_PCLKDBG_DESC 0x310
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#define A72_CRM_CLOCK_MODE_CONTROL 0x40
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#define A72_CRM_CLOCK_MODE_CONTROL__CLK_CHANGE_TRIGGER 0
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#define A72_CRM_CLOCK_CONTROL_0 0x200
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#define A72_CRM_CLOCK_CONTROL_0__ARM_HW_SW_ENABLE_SEL 0
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#define A72_CRM_CLOCK_CONTROL_0__AXI_HW_SW_ENABLE_SEL 2
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#define A72_CRM_CLOCK_CONTROL_0__ACP_HW_SW_ENABLE_SEL 4
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#define A72_CRM_CLOCK_CONTROL_0__ATB_HW_SW_ENABLE_SEL 6
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#define A72_CRM_CLOCK_CONTROL_0__PCLKDBG_HW_SW_ENA_SEL 8
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#define A72_CRM_CLOCK_CONTROL_1 0x204
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#define A72_CRM_CLOCK_CONTROL_1__TMON_HW_SW_ENABLE_SEL 6
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#define A72_CRM_CLOCK_CONTROL_1__APB_HW_SW_ENABLE_SEL 8
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#define A72_CRM_SOFTRESETN_0__CRYSTAL26_SOFTRESETN 0
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#define A72_CRM_SOFTRESETN_0__CRM_PLL0_SOFTRESETN 1
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#define A72_CRM_SOFTRESETN_0__AXI_SOFTRESETN 9
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#define A72_CRM_SOFTRESETN_0__ACP_SOFTRESETN 10
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#define A72_CRM_SOFTRESETN_0__ATB_SOFTRESETN 11
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#define A72_CRM_SOFTRESETN_0__PCLKDBG_SOFTRESETN 12
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#define A72_CRM_SOFTRESETN_0__TMON_SOFTRESETN 15
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#define A72_CRM_SOFTRESETN_0__L2_SOFTRESETN 3
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#define A72_CRM_SOFTRESETN_1__APB_SOFTRESETN 8
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/* core related regs */
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#define A72_CRM_DOMAIN_0_CONTROL 0x800
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#define A72_CRM_DOMAIN_0_CONTROL__DOMAIN_0_ISO_MEM 0x6
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#define A72_CRM_DOMAIN_0_CONTROL__DOMAIN_0_ISO_I_O 0x0
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#define A72_CRM_DOMAIN_1_CONTROL 0x804
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#define A72_CRM_DOMAIN_1_CONTROL__DOMAIN_1_ISO_MEM 0x6
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#define A72_CRM_DOMAIN_1_CONTROL__DOMAIN_1_ISO_I_O 0x0
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#define A72_CRM_CORE_CONFIG_RVBA0_LO 0xD10
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#define A72_CRM_CORE_CONFIG_RVBA0_MID 0xD14
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#define A72_CRM_CORE_CONFIG_RVBA0_HI 0xD18
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#define A72_CRM_CORE_CONFIG_RVBA1_LO 0xD20
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#define A72_CRM_CORE_CONFIG_RVBA1_MID 0xD24
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#define A72_CRM_CORE_CONFIG_RVBA1_HI 0xD28
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#define A72_CRM_SUBSYSTEM_CONFIG_0 0xC80
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#define A72_CRM_SUBSYSTEM_CONFIG_0__DBGPWRDUP_CFG_SHIFT 4
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#define A72_CRM_SOFTRESETN_0__COREPOR0_SOFTRESETN 4
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#define A72_CRM_SOFTRESETN_0__COREPOR1_SOFTRESETN 5
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#define A72_CRM_SOFTRESETN_1__CORE0_SOFTRESETN 0
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#define A72_CRM_SOFTRESETN_1__DEBUG0_SOFTRESETN 4
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#define A72_CRM_SOFTRESETN_1__CORE1_SOFTRESETN 1
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#define A72_CRM_SOFTRESETN_1__DEBUG1_SOFTRESETN 5
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#define SPROC_MEMORY_BISR 0
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static int cluster_power_status[PLAT_BRCM_CLUSTER_COUNT] = {CLUSTER_POWER_ON,
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CLUSTER_POWER_OFF,
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CLUSTER_POWER_OFF,
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CLUSTER_POWER_OFF};
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void ihost_power_on_cluster(u_register_t mpidr)
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{
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uint32_t rst, d2xs;
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uint32_t cluster_id;
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uint32_t ihost_base;
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#if SPROC_MEMORY_BISR
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uint32_t bisr, cnt;
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#endif
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cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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uint32_t cluster0_freq_sel;
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if (cluster_power_status[cluster_id] == CLUSTER_POWER_ON)
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return;
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cluster_power_status[cluster_id] = CLUSTER_POWER_ON;
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INFO("enabling Cluster #%u\n", cluster_id);
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switch (cluster_id) {
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case 1:
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rst = (1 << CDRU_MISC_RESET_CONTROL__CDRU_IH1_RESET);
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d2xs = (1 << CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST1);
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#if SPROC_MEMORY_BISR
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bisr = CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST1;
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#endif
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break;
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case 2:
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rst = (1 << CDRU_MISC_RESET_CONTROL__CDRU_IH2_RESET);
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d2xs = (1 << CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST2);
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#if SPROC_MEMORY_BISR
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bisr = CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST2;
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#endif
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break;
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case 3:
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rst = (1 << CDRU_MISC_RESET_CONTROL__CDRU_IH3_RESET);
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d2xs = (1 << CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST3);
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#if SPROC_MEMORY_BISR
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bisr = CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST3;
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#endif
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break;
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default:
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ERROR("Invalid cluster :%u\n", cluster_id);
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return;
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}
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/* Releasing ihost resets */
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mmio_setbits_32(CDRU_MISC_RESET_CONTROL, rst);
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/* calculate cluster/ihost base address */
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ihost_base = IHOST0_BASE + cluster_id * IHOST_ADDR_SPACE;
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/* Remove Cluster IO isolation */
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mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_4_CONTROL,
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(1 << A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_I_O),
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(1 << A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_DFT) |
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(1 << A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_MEM));
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/*
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* Since BISR sequence requires that all cores of cluster should
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* have removed I/O isolation hence doing same here.
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*/
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/* Remove core0 memory IO isolations */
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mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_0_CONTROL,
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(1 << A72_CRM_DOMAIN_0_CONTROL__DOMAIN_0_ISO_I_O),
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(1 << A72_CRM_DOMAIN_0_CONTROL__DOMAIN_0_ISO_MEM));
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/* Remove core1 memory IO isolations */
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mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_1_CONTROL,
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(1 << A72_CRM_DOMAIN_1_CONTROL__DOMAIN_1_ISO_I_O),
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(1 << A72_CRM_DOMAIN_1_CONTROL__DOMAIN_1_ISO_MEM));
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#if SPROC_MEMORY_BISR
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mmio_setbits_32(CRMU_BISR_PDG_MASK, (1 << bisr));
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if (!(mmio_read_32(CDRU_CHIP_STRAP_DATA_LSW) &
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(1 << CDRU_CHIP_STRAP_DATA_LSW__BISR_BYPASS_MODE))) {
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/* BISR completion would take max 2 usec */
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cnt = 0;
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while (cnt < 2) {
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udelay(1);
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if (mmio_read_32(CRMU_CHIP_OTPC_STATUS) &
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(1 << CRMU_CHIP_OTPC_STATUS__OTP_BISR_LOAD_DONE))
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break;
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cnt++;
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}
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}
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/* if BISR is not completed, need to be checked with ASIC team */
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if (((mmio_read_32(CRMU_CHIP_OTPC_STATUS)) &
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(1 << CRMU_CHIP_OTPC_STATUS__OTP_BISR_LOAD_DONE)) == 0) {
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WARN("BISR did not completed and need to be addressed\n");
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}
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#endif
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/* PLL Power up. supply is already on. Turn on PLL LDO/PWR */
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mmio_write_32(ihost_base + A72_CRM_PLL_PWR_ON,
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(1 << A72_CRM_PLL_PWR_ON__PLL0_ISO_PLLOUT) |
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(1 << A72_CRM_PLL_PWR_ON__PLL0_PWRON_LDO) |
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(1 << A72_CRM_PLL_PWR_ON__PLL0_PWRON_PLL));
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/* 1us in spec; Doubling it to be safe*/
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udelay(2);
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/* Remove PLL output ISO */
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mmio_write_32(ihost_base + A72_CRM_PLL_PWR_ON,
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(1 << A72_CRM_PLL_PWR_ON__PLL0_PWRON_LDO) |
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(1 << A72_CRM_PLL_PWR_ON__PLL0_PWRON_PLL));
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/*
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* PLL0 Configuration Control Register
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* these 4 registers drive the i_pll_ctrl[63:0] input of pll
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* (16b per register).
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* the values are derived from the spec (sections 8 and 10).
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*/
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mmio_write_32(ihost_base + A72_CRM_PLL0_CFG0_CTRL, 0x00000000);
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mmio_write_32(ihost_base + A72_CRM_PLL0_CFG1_CTRL, 0x00008400);
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mmio_write_32(ihost_base + A72_CRM_PLL0_CFG2_CTRL, 0x00000001);
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mmio_write_32(ihost_base + A72_CRM_PLL0_CFG3_CTRL, 0x00000000);
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/* Read the freq_sel from cluster 0, which is up already */
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cluster0_freq_sel = bcm_get_ihost_pll_freq(0);
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bcm_set_ihost_pll_freq(cluster_id, cluster0_freq_sel);
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udelay(1);
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/* Release clock source reset */
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mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0,
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(1 << A72_CRM_SOFTRESETN_0__CRYSTAL26_SOFTRESETN) |
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(1 << A72_CRM_SOFTRESETN_0__CRM_PLL0_SOFTRESETN));
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udelay(1);
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/*
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* Integer division for clks (divider value = n+1).
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* These are the divisor of ARM PLL clock frequecy.
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*/
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mmio_write_32(ihost_base + A72_CRM_AXI_CLK_DESC, 0x00000001);
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mmio_write_32(ihost_base + A72_CRM_ACP_CLK_DESC, 0x00000001);
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mmio_write_32(ihost_base + A72_CRM_ATB_CLK_DESC, 0x00000004);
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mmio_write_32(ihost_base + A72_CRM_PCLKDBG_DESC, 0x0000000b);
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/*
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* clock change trigger - must set to take effect after clock
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* source change
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*/
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mmio_setbits_32(ihost_base + A72_CRM_CLOCK_MODE_CONTROL,
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(1 << A72_CRM_CLOCK_MODE_CONTROL__CLK_CHANGE_TRIGGER));
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/* turn on functional clocks */
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mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_0,
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(3 << A72_CRM_CLOCK_CONTROL_0__ARM_HW_SW_ENABLE_SEL) |
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(3 << A72_CRM_CLOCK_CONTROL_0__AXI_HW_SW_ENABLE_SEL) |
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(3 << A72_CRM_CLOCK_CONTROL_0__ACP_HW_SW_ENABLE_SEL) |
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(3 << A72_CRM_CLOCK_CONTROL_0__ATB_HW_SW_ENABLE_SEL) |
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(3 << A72_CRM_CLOCK_CONTROL_0__PCLKDBG_HW_SW_ENA_SEL));
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mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_1,
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(3 << A72_CRM_CLOCK_CONTROL_1__TMON_HW_SW_ENABLE_SEL) |
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(3 << A72_CRM_CLOCK_CONTROL_1__APB_HW_SW_ENABLE_SEL));
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/* Program D2XS Power Down Registers */
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mmio_setbits_32(CDRU_CCN_REGISTER_CONTROL_1, d2xs);
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/* Program Core Config Debug ROM Address Registers */
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/* mark valid for Debug ROM base address */
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_DBGCTRL,
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(1 << A72_CRM_CORE_CONFIG_DBGCTRL__DBGROMADDRV));
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/* Program Lo and HI address of coresight DBG rom address */
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_DBGROM_LO,
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(CORESIGHT_BASE_ADDR >> 12) & 0xffff);
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_DBGROM_HI,
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(CORESIGHT_BASE_ADDR >> 28) & 0xffff);
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/*
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* Release soft resets of different components.
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* Order: Bus clocks --> PERIPH --> L2 --> cores
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*/
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/* Bus clocks soft resets */
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mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0,
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(1 << A72_CRM_SOFTRESETN_0__CRYSTAL26_SOFTRESETN) |
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(1 << A72_CRM_SOFTRESETN_0__CRM_PLL0_SOFTRESETN) |
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(1 << A72_CRM_SOFTRESETN_0__AXI_SOFTRESETN) |
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(1 << A72_CRM_SOFTRESETN_0__ACP_SOFTRESETN) |
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(1 << A72_CRM_SOFTRESETN_0__ATB_SOFTRESETN) |
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(1 << A72_CRM_SOFTRESETN_0__PCLKDBG_SOFTRESETN));
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mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_1,
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(1 << A72_CRM_SOFTRESETN_1__APB_SOFTRESETN));
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/* Periph component softreset */
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mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0,
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(1 << A72_CRM_SOFTRESETN_0__TMON_SOFTRESETN));
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/* L2 softreset */
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mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0,
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(1 << A72_CRM_SOFTRESETN_0__L2_SOFTRESETN));
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/* Enable and program Satellite timer */
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ihost_enable_satellite_timer(cluster_id);
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}
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void ihost_power_on_secondary_core(u_register_t mpidr, uint64_t rvbar)
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{
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uint32_t ihost_base;
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uint32_t coreid = MPIDR_AFFLVL0_VAL(mpidr);
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uint32_t cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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ihost_base = IHOST0_BASE + cluster_id * IHOST_ADDR_SPACE;
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INFO("programming core #%u\n", coreid);
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if (coreid) {
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/* program the entry point for core1 */
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA1_LO,
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rvbar & 0xFFFF);
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA1_MID,
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(rvbar >> 16) & 0xFFFF);
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA1_HI,
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(rvbar >> 32) & 0xFFFF);
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} else {
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/* program the entry point for core */
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA0_LO,
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rvbar & 0xFFFF);
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA0_MID,
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(rvbar >> 16) & 0xFFFF);
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mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA0_HI,
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(rvbar >> 32) & 0xFFFF);
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}
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/* Tell debug logic which processor is up */
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mmio_setbits_32(ihost_base + A72_CRM_SUBSYSTEM_CONFIG_0,
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(coreid ?
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(2 << A72_CRM_SUBSYSTEM_CONFIG_0__DBGPWRDUP_CFG_SHIFT) :
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(1 << A72_CRM_SUBSYSTEM_CONFIG_0__DBGPWRDUP_CFG_SHIFT)));
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/* releasing soft resets for IHOST core */
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mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0,
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(coreid ?
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(1 << A72_CRM_SOFTRESETN_0__COREPOR1_SOFTRESETN) :
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(1 << A72_CRM_SOFTRESETN_0__COREPOR0_SOFTRESETN)));
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mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_1,
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(coreid ?
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((1 << A72_CRM_SOFTRESETN_1__CORE1_SOFTRESETN) |
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(1 << A72_CRM_SOFTRESETN_1__DEBUG1_SOFTRESETN)) :
|
|
((1 << A72_CRM_SOFTRESETN_1__CORE0_SOFTRESETN) |
|
|
(1 << A72_CRM_SOFTRESETN_1__DEBUG0_SOFTRESETN))));
|
|
}
|