132 lines
3.5 KiB
C
132 lines
3.5 KiB
C
/*
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* Copyright (c) 2015 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/ccn.h>
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#include <drivers/delay_timer.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <lib/spinlock.h>
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#include <plat/common/platform.h>
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#ifdef USE_PAXC
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#include <chimp.h>
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#endif
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#include <cmn_plat_util.h>
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#include <ihost_pm.h>
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#include <plat_brcm.h>
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#include <platform_def.h>
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static uint64_t plat_sec_entrypoint;
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/*******************************************************************************
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* SR handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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static int brcm_pwr_domain_on(u_register_t mpidr)
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{
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int cpuid;
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cpuid = plat_brcm_calc_core_pos(mpidr);
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INFO("mpidr :%lu, cpuid:%d\n", mpidr, cpuid);
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#ifdef USE_SINGLE_CLUSTER
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if (cpuid > 1)
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return PSCI_E_INTERN_FAIL;
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#endif
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ihost_power_on_cluster(mpidr);
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ihost_power_on_secondary_core(mpidr, plat_sec_entrypoint);
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* SR handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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static void brcm_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr());
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assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
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PLAT_LOCAL_STATE_OFF);
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if (target_state->pwr_domain_state[MPIDR_AFFLVL1] ==
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PLAT_LOCAL_STATE_OFF) {
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INFO("Cluster #%lu entering to snoop/dvm domain\n", cluster_id);
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ccn_enter_snoop_dvm_domain(1 << cluster_id);
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}
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/* Enable the gic cpu interface */
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plat_brcm_gic_pcpu_init();
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/* Program the gic per-cpu distributor or re-distributor interface */
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plat_brcm_gic_cpuif_enable();
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INFO("Gic Initialization done for this affinity instance\n");
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}
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static void __dead2 brcm_system_reset(void)
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{
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uint32_t reset_type = SOFT_SYS_RESET_L1;
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#ifdef USE_PAXC
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if (bcm_chimp_is_nic_mode())
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reset_type = SOFT_RESET_L3;
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#endif
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INFO("System rebooting - L%d...\n", reset_type);
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plat_soft_reset(reset_type);
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/* Prevent the function to return due to the attribute */
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while (1)
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;
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}
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static int brcm_system_reset2(int is_vendor, int reset_type,
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u_register_t cookie)
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{
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INFO("System rebooting - L%d...\n", reset_type);
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plat_soft_reset(reset_type);
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/*
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* plat_soft_reset cannot return (it is a __dead function),
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* but brcm_system_reset2 has to return some value, even in
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* this case.
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*/
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return 0;
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}
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/*******************************************************************************
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* Export the platform handlers via plat_brcm_psci_pm_ops. The ARM Standard
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* platform will take care of registering the handlers with PSCI.
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******************************************************************************/
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const plat_psci_ops_t plat_brcm_psci_pm_ops = {
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.pwr_domain_on = brcm_pwr_domain_on,
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.pwr_domain_on_finish = brcm_pwr_domain_on_finish,
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.system_reset = brcm_system_reset,
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.system_reset2 = brcm_system_reset2
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &plat_brcm_psci_pm_ops;
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plat_sec_entrypoint = sec_entrypoint;
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return 0;
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}
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