92 lines
2.3 KiB
C
92 lines
2.3 KiB
C
/*
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <drivers/arm/gicv3.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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/* The GICv3 driver only needs to be initialized in EL3 */
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static uintptr_t brcm_rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static const interrupt_prop_t brcm_interrupt_props[] = {
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/* G1S interrupts */
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PLAT_BRCM_G1S_IRQ_PROPS(INTR_GROUP1S),
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/* G0 interrupts */
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PLAT_BRCM_G0_IRQ_PROPS(INTR_GROUP0)
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};
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/*
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* MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
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* to core position.
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*
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* Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
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* values read from GICR_TYPER don't have an MT field. To reuse the same
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* translation used for CPUs, we insert MT bit read from the PE's MPIDR into
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* that read from GICR_TYPER.
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*
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* Assumptions:
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*
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* - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
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* - No CPUs implemented in the system use affinity level 3.
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*/
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static unsigned int brcm_gicv3_mpidr_hash(u_register_t mpidr)
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{
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mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
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return plat_core_pos_by_mpidr(mpidr);
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}
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static const gicv3_driver_data_t brcm_gic_data = {
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.gicd_base = PLAT_BRCM_GICD_BASE,
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.gicr_base = PLAT_BRCM_GICR_BASE,
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.interrupt_props = brcm_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(brcm_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = brcm_rdistif_base_addrs,
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.mpidr_to_core_pos = brcm_gicv3_mpidr_hash
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};
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void plat_brcm_gic_driver_init(void)
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{
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/* TODO Check if this is required to be initialized here
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* after getting initialized in EL3, should we re-init this here
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* in S-EL1
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*/
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gicv3_driver_init(&brcm_gic_data);
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}
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void plat_brcm_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void plat_brcm_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void plat_brcm_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void plat_brcm_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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void plat_brcm_gic_redistif_on(void)
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{
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gicv3_rdistif_on(plat_my_core_pos());
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}
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void plat_brcm_gic_redistif_off(void)
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{
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gicv3_rdistif_off(plat_my_core_pos());
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}
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