Bipin Ravi 9b2510b69d fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 ... This patch applies CVE-2022-23960 workarounds for Cortex-A75, Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements the new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery hooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to enable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3 is implemented for A57/A72 because some revisions are affected by both CVE-2022-23960 and CVE-2017-5715 and this allows callers to replace SMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details of SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c		2022-03-18 01:01:34 +02:00
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aarch32	lib: cpus: aarch32: sanity check pointers before use	2021-02-23 15:16:51 +01:00
aarch64	fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57	2022-03-18 01:01:34 +02:00
cpu-ops.mk	fix(security): workaround for CVE-2022-23960	2022-03-10 23:57:14 -06:00
errata_report.c	fix(errata_report): correct typo	2021-10-06 17:35:39 +02:00