1388 lines
27 KiB
ArmAsm
1388 lines
27 KiB
ArmAsm
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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.section .text, "ax"
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#include <asm_macros.S>
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#include <lib/psci/psci.h>
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#include <nxp_timer.h>
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#include <plat_gic.h>
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#include <pmu.h>
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#include <bl31_data.h>
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#include <plat_psci.h>
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#include <platform_def.h>
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.global soc_init_lowlevel
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.global soc_init_percpu
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.global _set_platform_security
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.global _soc_set_start_addr
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.global _soc_core_release
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.global _soc_ck_disabled
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.global _soc_core_restart
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.global _soc_core_prep_off
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.global _soc_core_entr_off
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.global _soc_core_exit_off
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.global _soc_sys_reset
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.global _soc_sys_off
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.global _soc_core_prep_stdby
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.global _soc_core_entr_stdby
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.global _soc_core_exit_stdby
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.global _soc_core_prep_pwrdn
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.global _soc_core_entr_pwrdn
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.global _soc_core_exit_pwrdn
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.global _soc_clstr_prep_stdby
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.global _soc_clstr_exit_stdby
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.global _soc_clstr_prep_pwrdn
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.global _soc_clstr_exit_pwrdn
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.global _soc_sys_prep_stdby
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.global _soc_sys_exit_stdby
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.global _soc_sys_prep_pwrdn
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.global _soc_sys_pwrdn_wfi
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.global _soc_sys_exit_pwrdn
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.equ TZPCDECPROT_0_SET_BASE, 0x02200804
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.equ TZPCDECPROT_1_SET_BASE, 0x02200810
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.equ TZPCDECPROT_2_SET_BASE, 0x0220081C
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.equ TZASC_REGION_ATTRIBUTES_0_0, 0x01100110
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/*
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* This function initialize the soc.
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* in: void
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* out: void
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* uses x0 - x11
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*/
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func soc_init_lowlevel
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/*
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* Called from C, so save the non-volatile regs
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* save these as pairs of registers to maintain the
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* required 16-byte alignment on the stack
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*/
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stp x4, x5, [sp, #-16]!
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stp x6, x7, [sp, #-16]!
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stp x8, x9, [sp, #-16]!
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stp x10, x11, [sp, #-16]!
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stp x12, x13, [sp, #-16]!
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stp x18, x30, [sp, #-16]!
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/*
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* Make sure the personality has been established by releasing cores
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* that are marked "to-be-disabled" from reset
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*/
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bl release_disabled /* 0-8 */
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/* Set SCRATCHRW7 to 0x0 */
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ldr x0, =DCFG_SCRATCHRW7_OFFSET
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mov x1, xzr
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bl _write_reg_dcfg
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/* Restore the aarch32/64 non-volatile registers */
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ldp x18, x30, [sp], #16
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ldp x12, x13, [sp], #16
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ldp x10, x11, [sp], #16
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ldp x8, x9, [sp], #16
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ldp x6, x7, [sp], #16
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ldp x4, x5, [sp], #16
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ret
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endfunc soc_init_lowlevel
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/*
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* void soc_init_percpu(void)
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*
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* This function performs any soc-specific initialization that is needed on
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* a per-core basis
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* in: none
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* out: none
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* uses x0 - x3
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*/
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func soc_init_percpu
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stp x4, x30, [sp, #-16]!
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bl plat_my_core_mask
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mov x2, x0
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/* x2 = core mask */
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/* see if this core is marked for prefetch disable */
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mov x0, #PREFETCH_DIS_OFFSET
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bl _get_global_data /* 0-1 */
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tst x0, x2
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b.eq 1f
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bl _disable_ldstr_pfetch_A72 /* 0 */
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1:
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mov x0, #NXP_PMU_ADDR
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bl enable_timer_base_to_cluster
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ldp x4, x30, [sp], #16
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ret
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endfunc soc_init_percpu
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/*
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* This function determines if a core is disabled via COREDISABLEDSR
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* in: w0 = core_mask_lsb
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* out: w0 = 0, core not disabled
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* w0 != 0, core disabled
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* uses x0, x1
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*/
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func _soc_ck_disabled
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/* get base addr of dcfg block */
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ldr x1, =NXP_DCFG_ADDR
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/* read COREDISABLEDSR */
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ldr w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
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/* test core bit */
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and w0, w1, w0
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ret
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endfunc _soc_ck_disabled
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/*
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* This function sets the security mechanisms in the SoC to implement the
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* Platform Security Policy
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*/
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func _set_platform_security
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mov x3, x30
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#if (!SUPPRESS_TZC)
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/* initialize the tzpc */
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bl init_tzpc
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#endif
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#if (!SUPPRESS_SEC)
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/* initialize secmon */
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bl initSecMon
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#endif
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mov x30, x3
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ret
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endfunc _set_platform_security
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/*
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* Part of CPU_ON
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*
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* This function releases a secondary core from reset
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* in: x0 = core_mask_lsb
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* out: none
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* uses: x0 - x3
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*/
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_soc_core_release:
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mov x3, x30
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/*
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* Write to CORE_HOLD to tell the bootrom that we want this core
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* to run
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*/
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ldr x1, =NXP_SEC_REGFILE_ADDR
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str w0, [x1, #CORE_HOLD_OFFSET]
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/* Read-modify-write BRRL to release core */
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mov x1, #NXP_RESET_ADDR
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ldr w2, [x1, #BRR_OFFSET]
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orr w2, w2, w0
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str w2, [x1, #BRR_OFFSET]
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dsb sy
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isb
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/* Send event */
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sev
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isb
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mov x30, x3
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ret
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/*
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* This function writes a 64-bit address to bootlocptrh/l
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* in: x0, 64-bit address to write to BOOTLOCPTRL/H
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* uses x0, x1, x2
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*/
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func _soc_set_start_addr
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/* Get the 64-bit base address of the dcfg block */
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ldr x2, =NXP_DCFG_ADDR
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/* Write the 32-bit BOOTLOCPTRL register */
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mov x1, x0
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str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
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/* Write the 32-bit BOOTLOCPTRH register */
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lsr x1, x0, #32
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str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
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ret
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endfunc _soc_set_start_addr
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/*
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* Part of CPU_ON
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*
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* This function restarts a core shutdown via _soc_core_entr_off
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* in: x0 = core mask lsb (of the target cpu)
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* out: x0 == 0, on success
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* x0 != 0, on failure
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* uses x0 - x6
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*/
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_soc_core_restart:
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mov x6, x30
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mov x4, x0
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/* pgm GICD_CTLR - enable secure grp0 */
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mov x5, #NXP_GICD_ADDR
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ldr w2, [x5, #GICD_CTLR_OFFSET]
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orr w2, w2, #GICD_CTLR_EN_GRP_0
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str w2, [x5, #GICD_CTLR_OFFSET]
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dsb sy
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isb
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/* Poll on RWP til write completes */
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4:
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ldr w2, [x5, #GICD_CTLR_OFFSET]
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tst w2, #GICD_CTLR_RWP
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b.ne 4b
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/*
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* x4 = core mask lsb
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* x5 = gicd base addr
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*/
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mov x0, x4
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bl get_mpidr_value
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/* Generate target list bit */
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and x1, x0, #MPIDR_AFFINITY0_MASK
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mov x2, #1
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lsl x2, x2, x1
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/* Get the affinity1 field */
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and x1, x0, #MPIDR_AFFINITY1_MASK
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lsl x1, x1, #8
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orr x2, x2, x1
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/* Insert the INTID for SGI15 */
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orr x2, x2, #ICC_SGI0R_EL1_INTID
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/* Fire the SGI */
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msr ICC_SGI0R_EL1, x2
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dsb sy
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isb
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/* Load '0' on success */
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mov x0, xzr
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mov x30, x6
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ret
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/*
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* Part of CPU_OFF
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*
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* This function programs SoC & GIC registers in preparation for shutting down
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* the core
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* in: x0 = core mask lsb
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* out: none
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* uses x0 - x7
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*/
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_soc_core_prep_off:
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mov x8, x30
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mov x7, x0
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/* x7 = core mask lsb */
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mrs x1, CPUECTLR_EL1
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/* Set smp and disable L2 snoops in cpuectlr */
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orr x1, x1, #CPUECTLR_SMPEN_EN
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orr x1, x1, #CPUECTLR_DISABLE_TWALK_PREFETCH
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bic x1, x1, #CPUECTLR_INS_PREFETCH_MASK
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bic x1, x1, #CPUECTLR_DAT_PREFETCH_MASK
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/* Set retention control in cpuectlr */
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bic x1, x1, #CPUECTLR_TIMER_MASK
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orr x1, x1, #CPUECTLR_TIMER_2TICKS
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msr CPUECTLR_EL1, x1
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/* Get redistributor rd base addr for this core */
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mov x0, x7
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bl get_gic_rd_base
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mov x6, x0
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/* Get redistributor sgi base addr for this core */
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mov x0, x7
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bl get_gic_sgi_base
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mov x5, x0
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/*
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* x5 = gicr sgi base addr
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* x6 = gicr rd base addr
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* x7 = core mask lsb
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*/
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/* Disable SGI 15 at redistributor - GICR_ICENABLER0 */
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mov w3, #GICR_ICENABLER0_SGI15
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str w3, [x5, #GICR_ICENABLER0_OFFSET]
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2:
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/* Poll on rwp bit in GICR_CTLR */
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ldr w4, [x6, #GICR_CTLR_OFFSET]
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tst w4, #GICR_CTLR_RWP
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b.ne 2b
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/* Disable GRP1 interrupts at cpu interface */
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msr ICC_IGRPEN1_EL3, xzr
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/* Disable GRP0 ints at cpu interface */
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msr ICC_IGRPEN0_EL1, xzr
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/* Program the redistributor - poll on GICR_CTLR.RWP as needed */
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/* Define SGI 15 as Grp0 - GICR_IGROUPR0 */
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ldr w4, [x5, #GICR_IGROUPR0_OFFSET]
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bic w4, w4, #GICR_IGROUPR0_SGI15
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str w4, [x5, #GICR_IGROUPR0_OFFSET]
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/* Define SGI 15 as Grp0 - GICR_IGRPMODR0 */
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ldr w3, [x5, #GICR_IGRPMODR0_OFFSET]
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bic w3, w3, #GICR_IGRPMODR0_SGI15
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str w3, [x5, #GICR_IGRPMODR0_OFFSET]
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/* Set priority of SGI 15 to highest (0x0) - GICR_IPRIORITYR3 */
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ldr w4, [x5, #GICR_IPRIORITYR3_OFFSET]
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bic w4, w4, #GICR_IPRIORITYR3_SGI15_MASK
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str w4, [x5, #GICR_IPRIORITYR3_OFFSET]
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/* Enable SGI 15 at redistributor - GICR_ISENABLER0 */
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mov w3, #GICR_ISENABLER0_SGI15
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str w3, [x5, #GICR_ISENABLER0_OFFSET]
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dsb sy
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isb
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3:
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/* Poll on rwp bit in GICR_CTLR */
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ldr w4, [x6, #GICR_CTLR_OFFSET]
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tst w4, #GICR_CTLR_RWP
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b.ne 3b
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/* Quiesce the debug interfaces */
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mrs x3, osdlr_el1
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orr x3, x3, #OSDLR_EL1_DLK_LOCK
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msr osdlr_el1, x3
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isb
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/* Enable grp0 ints */
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mov x3, #ICC_IGRPEN0_EL1_EN
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msr ICC_IGRPEN0_EL1, x3
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/*
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* x5 = gicr sgi base addr
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* x6 = gicr rd base addr
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* x7 = core mask lsb
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*/
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/* Clear any pending interrupts */
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mvn w1, wzr
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str w1, [x5, #GICR_ICPENDR0_OFFSET]
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/* Make sure system counter is enabled */
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ldr x3, =NXP_TIMER_ADDR
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ldr w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
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tst w0, #SYS_COUNTER_CNTCR_EN
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b.ne 4f
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orr w0, w0, #SYS_COUNTER_CNTCR_EN
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str w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
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4:
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/* Enable the core timer and mask timer interrupt */
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mov x1, #CNTP_CTL_EL0_EN
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orr x1, x1, #CNTP_CTL_EL0_IMASK
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msr cntp_ctl_el0, x1
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isb
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mov x30, x8
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ret
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/*
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* Part of CPU_OFF
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*
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* This function performs the final steps to shutdown the core
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* in: x0 = core mask lsb
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* out: none
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* uses x0 - x5
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*/
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_soc_core_entr_off:
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mov x5, x30
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mov x4, x0
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/* x4 = core mask */
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1:
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/* Enter low-power state by executing wfi */
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wfi
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/* See if SGI15 woke us up */
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mrs x2, ICC_IAR0_EL1
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mov x3, #ICC_IAR0_EL1_SGI15
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cmp x2, x3
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b.ne 1b
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/* Deactivate the int */
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msr ICC_EOIR0_EL1, x2
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/* x4 = core mask */
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2:
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/* Check if core has been turned on */
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mov x0, x4
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bl _getCoreState
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/* x0 = core state */
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cmp x0, #CORE_WAKEUP
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b.ne 1b
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/* If we get here, then we have exited the wfi */
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mov x30, x5
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ret
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/*
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* Part of CPU_OFF
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*
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* This function starts the process of starting a core back up
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* in: x0 = core mask lsb
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* out: none
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* uses x0, x1, x2, x3, x4, x5, x6
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*/
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_soc_core_exit_off:
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mov x6, x30
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mov x5, x0
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/* Disable forwarding of GRP0 ints at cpu interface */
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msr ICC_IGRPEN0_EL1, xzr
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/* Get redistributor sgi base addr for this core */
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mov x0, x5
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bl get_gic_sgi_base
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mov x4, x0
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/* x4 = gicr sgi base addr */
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/* x5 = core mask */
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/* Disable SGI 15 at redistributor - GICR_ICENABLER0 */
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mov w1, #GICR_ICENABLER0_SGI15
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str w1, [x4, #GICR_ICENABLER0_OFFSET]
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/* Get redistributor rd base addr for this core */
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mov x0, x5
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bl get_gic_rd_base
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mov x4, x0
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/* x4 = gicr rd base addr */
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2:
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/* Poll on rwp bit in GICR_CTLR */
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ldr w2, [x4, #GICR_CTLR_OFFSET]
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tst w2, #GICR_CTLR_RWP
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b.ne 2b
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/* x4 = gicr rd base addr */
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/* Unlock the debug interfaces */
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mrs x3, osdlr_el1
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bic x3, x3, #OSDLR_EL1_DLK_LOCK
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msr osdlr_el1, x3
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isb
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dsb sy
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isb
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mov x30, x6
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ret
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/*
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* This function requests a reset of the entire SOC
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* in: none
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* out: none
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* uses: x0, x1, x2, x3, x4, x5, x6
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*/
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_soc_sys_reset:
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mov x3, x30
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/* Make sure the mask is cleared in the reset request mask register */
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mov x0, #RST_RSTRQMR1_OFFSET
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mov w1, wzr
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bl _write_reg_reset
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/* Set the reset request */
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mov x4, #RST_RSTCR_OFFSET
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mov x0, x4
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mov w1, #RSTCR_RESET_REQ
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bl _write_reg_reset
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/* x4 = RST_RSTCR_OFFSET */
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/*
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* Just in case this address range is mapped as cacheable,
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* flush the write out of the dcaches
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*/
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mov x2, #NXP_RESET_ADDR
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add x2, x2, x4
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dc cvac, x2
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dsb st
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isb
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/* This function does not return */
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1:
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wfi
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b 1b
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/*
|
|
* Part of SYSTEM_OFF
|
|
*
|
|
* This function turns off the SoC clocks
|
|
* Note: this function is not intended to return, and the only allowable
|
|
* recovery is POR
|
|
* in: none
|
|
* out: none
|
|
* uses x0, x1, x2, x3
|
|
*/
|
|
_soc_sys_off:
|
|
/*
|
|
* Disable sec, spi and flexspi
|
|
* TBD - Check if eNETC needs to be disabled
|
|
*/
|
|
ldr x2, =NXP_DCFG_ADDR
|
|
ldr x0, =DCFG_DEVDISR1_OFFSET
|
|
ldr w1, =DCFG_DEVDISR1_SEC
|
|
str w1, [x2, x0]
|
|
ldr x0, =DCFG_DEVDISR4_OFFSET
|
|
ldr w1, =DCFG_DEVDISR4_SPI_QSPI
|
|
str w1, [x2, x0]
|
|
|
|
/* Set TPMWAKEMR0 */
|
|
ldr x0, =TPMWAKEMR0_ADDR
|
|
mov w1, #0x1
|
|
str w1, [x0]
|
|
|
|
/* Disable icache, dcache, mmu @ EL1 */
|
|
mov x1, #SCTLR_I_C_M_MASK
|
|
mrs x0, sctlr_el1
|
|
bic x0, x0, x1
|
|
msr sctlr_el1, x0
|
|
|
|
/* Disable L2 prefetches */
|
|
mrs x0, CPUECTLR_EL1
|
|
orr x0, x0, #CPUECTLR_SMPEN_EN
|
|
bic x0, x0, #CPUECTLR_TIMER_MASK
|
|
orr x0, x0, #CPUECTLR_TIMER_2TICKS
|
|
msr CPUECTLR_EL1, x0
|
|
dsb sy
|
|
isb
|
|
|
|
/* Disable CCI snoop domain */
|
|
ldr x0, =NXP_CCI_ADDR
|
|
mov w1, #0x1
|
|
str w1, [x0]
|
|
|
|
bl get_pmu_idle_core_mask
|
|
|
|
/* x3 = pmu base addr */
|
|
mov x3, #NXP_PMU_ADDR
|
|
4:
|
|
ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
|
|
cmp w1, w0
|
|
b.ne 4b
|
|
|
|
bl get_pmu_idle_cluster_mask
|
|
mov x3, #NXP_PMU_ADDR
|
|
str w0, [x3, #PMU_CLAINACTSETR_OFFSET]
|
|
|
|
bl get_pmu_idle_core_mask
|
|
mov x3, #NXP_PMU_ADDR
|
|
1:
|
|
ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
|
|
cmp w1, w0
|
|
b.ne 1b
|
|
|
|
bl get_pmu_flush_cluster_mask
|
|
mov x3, #NXP_PMU_ADDR
|
|
str w0, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
|
|
2:
|
|
ldr w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
|
|
cmp w1, w0
|
|
b.ne 2b
|
|
|
|
str w0, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
|
|
|
|
str w0, [x3, #PMU_CLSINACTSETR_OFFSET]
|
|
|
|
mov x2, #DAIF_SET_MASK
|
|
mrs x1, spsr_el1
|
|
orr x1, x1, x2
|
|
msr spsr_el1, x1
|
|
|
|
mrs x1, spsr_el2
|
|
orr x1, x1, x2
|
|
msr spsr_el2, x1
|
|
|
|
/* Force the debug interface to be quiescent */
|
|
mrs x0, osdlr_el1
|
|
orr x0, x0, #0x1
|
|
msr osdlr_el1, x0
|
|
|
|
/* Invalidate all TLB entries at all 3 exception levels */
|
|
tlbi alle1
|
|
tlbi alle2
|
|
tlbi alle3
|
|
|
|
/* x3 = pmu base addr */
|
|
|
|
/* Request lpm20 */
|
|
ldr x0, =PMU_POWMGTCSR_OFFSET
|
|
ldr w1, =PMU_POWMGTCSR_VAL
|
|
str w1, [x3, x0]
|
|
isb
|
|
dsb sy
|
|
5:
|
|
wfe
|
|
b.eq 5b
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs SoC-specific programming prior to standby
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0, x1
|
|
*/
|
|
_soc_core_prep_stdby:
|
|
/* Clear CPUECTLR_EL1[2:0] */
|
|
mrs x1, CPUECTLR_EL1
|
|
bic x1, x1, #CPUECTLR_TIMER_MASK
|
|
msr CPUECTLR_EL1, x1
|
|
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function puts the calling core into standby state
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0
|
|
*/
|
|
_soc_core_entr_stdby:
|
|
/* X0 = core mask lsb */
|
|
dsb sy
|
|
isb
|
|
wfi
|
|
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs any SoC-specific cleanup after standby state
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses none
|
|
*/
|
|
_soc_core_exit_stdby:
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs SoC-specific programming prior to power-down
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0, x1, x2
|
|
*/
|
|
_soc_core_prep_pwrdn:
|
|
/* Make sure system counter is enabled */
|
|
ldr x2, =NXP_TIMER_ADDR
|
|
ldr w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
|
|
tst w0, #SYS_COUNTER_CNTCR_EN
|
|
b.ne 1f
|
|
orr w0, w0, #SYS_COUNTER_CNTCR_EN
|
|
str w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
|
|
1:
|
|
/*
|
|
* Enable dynamic retention control (CPUECTLR[2:0])
|
|
* Set the SMPEN bit (CPUECTLR[6])
|
|
*/
|
|
mrs x1, CPUECTLR_EL1
|
|
bic x1, x1, #CPUECTLR_RET_MASK
|
|
orr x1, x1, #CPUECTLR_TIMER_2TICKS
|
|
orr x1, x1, #CPUECTLR_SMPEN_EN
|
|
msr CPUECTLR_EL1, x1
|
|
|
|
isb
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function puts the calling core into a power-down state
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0
|
|
*/
|
|
_soc_core_entr_pwrdn:
|
|
/* X0 = core mask lsb */
|
|
dsb sy
|
|
isb
|
|
wfi
|
|
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs any SoC-specific cleanup after power-down state
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses none
|
|
*/
|
|
_soc_core_exit_pwrdn:
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs SoC-specific programming prior to standby
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0, x1
|
|
*/
|
|
_soc_clstr_prep_stdby:
|
|
/* Clear CPUECTLR_EL1[2:0] */
|
|
mrs x1, CPUECTLR_EL1
|
|
bic x1, x1, #CPUECTLR_TIMER_MASK
|
|
msr CPUECTLR_EL1, x1
|
|
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs any SoC-specific cleanup after standby state
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses none
|
|
*/
|
|
_soc_clstr_exit_stdby:
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs SoC-specific programming prior to power-down
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0, x1, x2
|
|
*/
|
|
_soc_clstr_prep_pwrdn:
|
|
/* Make sure system counter is enabled */
|
|
ldr x2, =NXP_TIMER_ADDR
|
|
ldr w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
|
|
tst w0, #SYS_COUNTER_CNTCR_EN
|
|
b.ne 1f
|
|
orr w0, w0, #SYS_COUNTER_CNTCR_EN
|
|
str w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
|
|
1:
|
|
/*
|
|
* Enable dynamic retention control (CPUECTLR[2:0])
|
|
* Set the SMPEN bit (CPUECTLR[6])
|
|
*/
|
|
mrs x1, CPUECTLR_EL1
|
|
bic x1, x1, #CPUECTLR_RET_MASK
|
|
orr x1, x1, #CPUECTLR_TIMER_2TICKS
|
|
orr x1, x1, #CPUECTLR_SMPEN_EN
|
|
msr CPUECTLR_EL1, x1
|
|
|
|
isb
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs any SoC-specific cleanup after power-down state
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses none
|
|
*/
|
|
_soc_clstr_exit_pwrdn:
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs SoC-specific programming prior to standby
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0, x1
|
|
*/
|
|
_soc_sys_prep_stdby:
|
|
/* Clear CPUECTLR_EL1[2:0] */
|
|
mrs x1, CPUECTLR_EL1
|
|
bic x1, x1, #CPUECTLR_TIMER_MASK
|
|
msr CPUECTLR_EL1, x1
|
|
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs any SoC-specific cleanup after standby state
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses none
|
|
*/
|
|
_soc_sys_exit_stdby:
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs SoC-specific programming prior to
|
|
* suspend-to-power-down
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0, x1, x2, x3, x4
|
|
*/
|
|
_soc_sys_prep_pwrdn:
|
|
/* Set retention control */
|
|
mrs x0, CPUECTLR_EL1
|
|
bic x0, x0, #CPUECTLR_TIMER_MASK
|
|
orr x0, x0, #CPUECTLR_TIMER_2TICKS
|
|
orr x0, x0, #CPUECTLR_SMPEN_EN
|
|
msr CPUECTLR_EL1, x0
|
|
dsb sy
|
|
isb
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function puts the calling core, and potentially the soc, into a
|
|
* low-power state
|
|
* in: x0 = core mask lsb
|
|
* out: x0 = 0, success
|
|
* x0 < 0, failure
|
|
* uses x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x13, x14, x15,
|
|
* x16, x17, x18
|
|
*/
|
|
_soc_sys_pwrdn_wfi:
|
|
mov x18, x30
|
|
|
|
mov x3, #NXP_PMU_ADDR
|
|
|
|
/* x3 = pmu base addr */
|
|
|
|
/* Backup epu registers to stack */
|
|
ldr x2, =NXP_EPU_ADDR
|
|
ldr w4, [x2, #EPU_EPIMCR10_OFFSET]
|
|
ldr w5, [x2, #EPU_EPCCR10_OFFSET]
|
|
ldr w6, [x2, #EPU_EPCTR10_OFFSET]
|
|
ldr w7, [x2, #EPU_EPGCR_OFFSET]
|
|
stp x4, x5, [sp, #-16]!
|
|
stp x6, x7, [sp, #-16]!
|
|
|
|
/*
|
|
* x2 = epu base addr
|
|
* x3 = pmu base addr
|
|
*/
|
|
|
|
/* Set up EPU event to receive the wake signal from PMU */
|
|
mov w4, #EPU_EPIMCR10_VAL
|
|
mov w5, #EPU_EPCCR10_VAL
|
|
mov w6, #EPU_EPCTR10_VAL
|
|
mov w7, #EPU_EPGCR_VAL
|
|
str w4, [x2, #EPU_EPIMCR10_OFFSET]
|
|
str w5, [x2, #EPU_EPCCR10_OFFSET]
|
|
str w6, [x2, #EPU_EPCTR10_OFFSET]
|
|
str w7, [x2, #EPU_EPGCR_OFFSET]
|
|
|
|
ldr x2, =NXP_GICD_ADDR
|
|
|
|
/*
|
|
* x2 = gicd base addr
|
|
* x3 = pmu base addr
|
|
*/
|
|
|
|
/* Backup flextimer/mmc/usb interrupt router */
|
|
ldr x0, =GICD_IROUTER60_OFFSET
|
|
ldr x1, =GICD_IROUTER76_OFFSET
|
|
ldr w4, [x2, x0]
|
|
ldr w5, [x2, x1]
|
|
ldr x0, =GICD_IROUTER112_OFFSET
|
|
ldr x1, =GICD_IROUTER113_OFFSET
|
|
ldr w6, [x2, x0]
|
|
ldr w7, [x2, x1]
|
|
stp x4, x5, [sp, #-16]!
|
|
stp x6, x7, [sp, #-16]!
|
|
|
|
/*
|
|
* x2 = gicd base addr
|
|
* x3 = pmu base addr
|
|
* x0 = GICD_IROUTER112_OFFSET
|
|
* x1 = GICD_IROUTER113_OFFSET
|
|
*/
|
|
|
|
/* Re-route interrupt to cluster 1 */
|
|
ldr w4, =GICD_IROUTER_VALUE
|
|
str w4, [x2, x0]
|
|
str w4, [x2, x1]
|
|
ldr x0, =GICD_IROUTER60_OFFSET
|
|
ldr x1, =GICD_IROUTER76_OFFSET
|
|
str w4, [x2, x0]
|
|
str w4, [x2, x1]
|
|
dsb sy
|
|
isb
|
|
|
|
/* x3 = pmu base addr */
|
|
|
|
/* Disable sec, Check for eNETC, spi and qspi */
|
|
ldr x2, =NXP_DCFG_ADDR
|
|
ldr x0, =DCFG_DEVDISR1_OFFSET
|
|
ldr w1, =DCFG_DEVDISR1_SEC
|
|
str w1, [x2, x0]
|
|
|
|
ldr x0, =DCFG_DEVDISR4_OFFSET
|
|
ldr w1, =DCFG_DEVDISR4_SPI_QSPI
|
|
str w1, [x2, x0]
|
|
|
|
/* x3 = pmu base addr */
|
|
|
|
/* Set TPMWAKEMR0 */
|
|
ldr x0, =TPMWAKEMR0_ADDR
|
|
mov w1, #0x1
|
|
str w1, [x0]
|
|
|
|
/* Disable CCI snoop domain */
|
|
ldr x0, =NXP_CCI_ADDR
|
|
mov w1, #0x1
|
|
str w1, [x0]
|
|
|
|
/* Setup retention control */
|
|
mrs x0, CPUECTLR_EL1
|
|
orr x0, x0, #CPUECTLR_SMPEN_EN
|
|
orr x0, x0, #CPUECTLR_TIMER_2TICKS
|
|
msr CPUECTLR_EL1, x0
|
|
dsb sy
|
|
isb
|
|
|
|
bl get_pmu_idle_core_mask
|
|
mov x3, #NXP_PMU_ADDR
|
|
8:
|
|
ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
|
|
cmp w1, w0
|
|
b.ne 8b
|
|
|
|
/* x3 = NXP_PMU_ADDR */
|
|
/* 1 cluster SoC */
|
|
|
|
bl get_pmu_idle_cluster_mask
|
|
mov x3, #NXP_PMU_ADDR
|
|
|
|
str w0, [x3, #PMU_CLAINACTSETR_OFFSET]
|
|
|
|
bl get_pmu_idle_core_mask
|
|
/* x3 = NXP_PMU_ADDR */
|
|
mov x3, #NXP_PMU_ADDR
|
|
1:
|
|
ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
|
|
cmp w1, w0
|
|
b.ne 1b
|
|
|
|
/* x3 = NXP_PMU_ADDR */
|
|
bl get_pmu_flush_cluster_mask
|
|
mov x3, #NXP_PMU_ADDR
|
|
|
|
str w0, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
|
|
|
|
/* x3 = NXP_PMU_ADDR */
|
|
2:
|
|
ldr w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
|
|
cmp w1, w0
|
|
b.ne 2b
|
|
|
|
/* x3 = NXP_PMU_ADDR */
|
|
|
|
str w0, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
|
|
|
|
str w0, [x3, #PMU_CLSINACTSETR_OFFSET]
|
|
|
|
/* Force the debug interface to be quiescent */
|
|
mrs x0, osdlr_el1
|
|
orr x0, x0, #0x1
|
|
msr osdlr_el1, x0
|
|
|
|
/*
|
|
* Enable the WakeRequest signal
|
|
* x3 is cpu mask starting from cpu1 to cpu0
|
|
*/
|
|
bl get_tot_num_cores
|
|
sub x0, x0, #1
|
|
mov x3, #0x1
|
|
lsl x3, x3, x0
|
|
2:
|
|
mov x0, x3
|
|
bl get_gic_rd_base // 0-2
|
|
ldr w1, [x0, #GICR_WAKER_OFFSET]
|
|
orr w1, w1, #GICR_WAKER_SLEEP_BIT
|
|
str w1, [x0, #GICR_WAKER_OFFSET]
|
|
1:
|
|
ldr w1, [x0, #GICR_WAKER_OFFSET]
|
|
cmp w1, #GICR_WAKER_ASLEEP
|
|
b.ne 1b
|
|
|
|
lsr x3, x3, #1
|
|
cbnz x3, 2b
|
|
|
|
/* Invalidate all TLB entries at all 3 exception levels */
|
|
tlbi alle1
|
|
tlbi alle2
|
|
tlbi alle3
|
|
|
|
/* Request lpm20 */
|
|
mov x3, #NXP_PMU_ADDR
|
|
ldr x0, =PMU_POWMGTCSR_OFFSET
|
|
ldr w1, =PMU_POWMGTCSR_VAL
|
|
str w1, [x3, x0]
|
|
|
|
ldr x5, =NXP_EPU_ADDR
|
|
4:
|
|
wfe
|
|
ldr w1, [x5, #EPU_EPCTR10_OFFSET]
|
|
cmp w1, #0
|
|
b.eq 4b
|
|
|
|
/* x3 = NXP_PMU_ADDR */
|
|
|
|
bl get_pmu_idle_cluster_mask
|
|
mov x3, NXP_PMU_ADDR
|
|
|
|
/* Re-enable the GPP ACP */
|
|
str w0, [x3, #PMU_CLAINACTCLRR_OFFSET]
|
|
str w0, [x3, #PMU_CLSINACTCLRR_OFFSET]
|
|
|
|
/* x3 = NXP_PMU_ADDR */
|
|
3:
|
|
ldr w1, [x3, #PMU_CLAINACTSETR_OFFSET]
|
|
cbnz w1, 3b
|
|
4:
|
|
ldr w1, [x3, #PMU_CLSINACTSETR_OFFSET]
|
|
cbnz w1, 4b
|
|
|
|
/*
|
|
* Enable the WakeRequest signal on cpu 0-1
|
|
* x3 is cpu mask starting from cpu1
|
|
*/
|
|
bl get_tot_num_cores
|
|
sub x0, x0, #1
|
|
mov x3, #0x1
|
|
lsl x3, x3, x0
|
|
2:
|
|
mov x0, x3
|
|
bl get_gic_rd_base // 0-2
|
|
ldr w1, [x0, #GICR_WAKER_OFFSET]
|
|
bic w1, w1, #GICR_WAKER_SLEEP_BIT
|
|
str w1, [x0, #GICR_WAKER_OFFSET]
|
|
1:
|
|
ldr w1, [x0, #GICR_WAKER_OFFSET]
|
|
cbnz w1, 1b
|
|
|
|
lsr x3, x3, #1
|
|
cbnz x3, 2b
|
|
|
|
/* Enable CCI snoop domain */
|
|
ldr x0, =NXP_CCI_ADDR
|
|
str wzr, [x0]
|
|
dsb sy
|
|
isb
|
|
|
|
ldr x3, =NXP_EPU_ADDR
|
|
|
|
/* x3 = epu base addr */
|
|
|
|
/* Enable sec, enetc, spi and qspi */
|
|
ldr x2, =NXP_DCFG_ADDR
|
|
str wzr, [x2, #DCFG_DEVDISR1_OFFSET]
|
|
str wzr, [x2, #DCFG_DEVDISR2_OFFSET]
|
|
str wzr, [x2, #DCFG_DEVDISR4_OFFSET]
|
|
|
|
/* Restore flextimer/mmc/usb interrupt router */
|
|
ldr x3, =NXP_GICD_ADDR
|
|
ldp x0, x2, [sp], #16
|
|
ldr x1, =GICD_IROUTER113_OFFSET
|
|
str w2, [x3, x1]
|
|
ldr x1, =GICD_IROUTER112_OFFSET
|
|
str w0, [x3, x1]
|
|
ldp x0, x2, [sp], #16
|
|
ldr x1, =GICD_IROUTER76_OFFSET
|
|
str w2, [x3, x1]
|
|
ldr x1, =GICD_IROUTER60_OFFSET
|
|
str w0, [x3, x1]
|
|
|
|
/* Restore EPU registers */
|
|
ldr x3, =NXP_EPU_ADDR
|
|
ldp x0, x2, [sp], #16
|
|
str w2, [x3, #EPU_EPGCR_OFFSET]
|
|
str w0, [x3, #EPU_EPCTR10_OFFSET]
|
|
ldp x2, x1, [sp], #16
|
|
str w1, [x3, #EPU_EPCCR10_OFFSET]
|
|
str w2, [x3, #EPU_EPIMCR10_OFFSET]
|
|
|
|
dsb sy
|
|
isb
|
|
mov x30, x18
|
|
ret
|
|
|
|
/*
|
|
* Part of CPU_SUSPEND
|
|
*
|
|
* This function performs any SoC-specific cleanup after power-down
|
|
* in: x0 = core mask lsb
|
|
* out: none
|
|
* uses x0, x1
|
|
*/
|
|
_soc_sys_exit_pwrdn:
|
|
/* Enable stack alignment checking */
|
|
mrs x1, SCTLR_EL1
|
|
orr x1, x1, #0x4
|
|
msr SCTLR_EL1, x1
|
|
|
|
/* Enable debug interface */
|
|
mrs x1, osdlr_el1
|
|
bic x1, x1, #OSDLR_EL1_DLK_LOCK
|
|
msr osdlr_el1, x1
|
|
|
|
/* Enable i-cache */
|
|
mrs x1, SCTLR_EL3
|
|
orr x1, x1, #SCTLR_I_MASK
|
|
msr SCTLR_EL3, x1
|
|
|
|
isb
|
|
ret
|
|
|
|
/*
|
|
* This function setc up the TrustZone Address Space Controller (TZASC)
|
|
* in: none
|
|
* out: none
|
|
* uses x0, x1
|
|
*/
|
|
init_tzpc:
|
|
/* Set Non Secure access for all devices protected via TZPC */
|
|
ldr x1, =TZPCDECPROT_0_SET_BASE /* decode Protection-0 Set Reg */
|
|
mov w0, #0xFF /* set decode region to NS, Bits[7:0] */
|
|
str w0, [x1]
|
|
|
|
ldr x1, =TZPCDECPROT_1_SET_BASE /* decode Protection-1 Set Reg */
|
|
mov w0, #0xFF /* set decode region to NS, Bits[7:0] */
|
|
str w0, [x1]
|
|
|
|
ldr x1, =TZPCDECPROT_2_SET_BASE /* decode Protection-2 Set Reg */
|
|
mov w0, #0xFF /* set decode region to NS, Bits[7:0] */
|
|
str w0, [x1]
|
|
|
|
/* entire SRAM as NS */
|
|
ldr x1, =NXP_OCRAM_TZPC_ADDR /* secure RAM region size Reg */
|
|
mov w0, #0x00000000 /* 0x00000000 = no secure region */
|
|
str w0, [x1]
|
|
|
|
ret
|
|
|
|
/*
|
|
* This function performs any needed initialization on SecMon for
|
|
* boot services
|
|
*/
|
|
initSecMon:
|
|
/* Read the register hpcomr */
|
|
ldr x1, =NXP_SNVS_ADDR
|
|
ldr w0, [x1, #SECMON_HPCOMR_OFFSET]
|
|
/* Turn off secure access for the privileged registers */
|
|
orr w0, w0, #SECMON_HPCOMR_NPSWAEN
|
|
/* Write back */
|
|
str w0, [x1, #SECMON_HPCOMR_OFFSET]
|
|
|
|
ret
|
|
|
|
/*
|
|
* This function checks to see if cores which are to be disabled have been
|
|
* released from reset - if not, it releases them
|
|
* in: none
|
|
* out: none
|
|
* uses x0, x1, x2, x3, x4, x5, x6, x7, x8
|
|
*/
|
|
release_disabled:
|
|
stp x18, x30, [sp, #-16]!
|
|
|
|
/*
|
|
* Get the number of cpus on this device
|
|
* Calling the below c function.
|
|
* No need to Callee saved registers x9-x15,
|
|
* as these registers are not used by the callee
|
|
* prior to calling the below C-routine.
|
|
*/
|
|
bl get_tot_num_cores
|
|
mov x6, x0
|
|
|
|
/* Read COREDISABLESR */
|
|
mov x0, #NXP_DCFG_ADDR
|
|
ldr w4, [x0, #DCFG_COREDISABLEDSR_OFFSET]
|
|
|
|
mov x0, #NXP_RESET_ADDR
|
|
ldr w5, [x0, #BRR_OFFSET]
|
|
|
|
/* Load the core mask for the first core */
|
|
mov x7, #1
|
|
|
|
/*
|
|
* x4 = COREDISABLESR
|
|
* x5 = BRR
|
|
* x6 = loop count
|
|
* x7 = core mask bit
|
|
*/
|
|
2:
|
|
/* Check if the core is to be disabled */
|
|
tst x4, x7
|
|
b.eq 1f
|
|
|
|
/* See if disabled cores have already been released from reset */
|
|
tst x5, x7
|
|
b.ne 1f
|
|
|
|
/* If core has not been released, then release it (0-3) */
|
|
mov x0, x7
|
|
bl _soc_core_release
|
|
|
|
/* Record the core state in the data area (0-3) */
|
|
mov x0, x7
|
|
mov x1, #CORE_DISABLED
|
|
bl _setCoreState
|
|
1:
|
|
/* Decrement the counter */
|
|
subs x6, x6, #1
|
|
b.le 3f
|
|
/* Shift the core mask to the next core */
|
|
lsl x7, x7, #1
|
|
/* Continue */
|
|
b 2b
|
|
3:
|
|
ldp x18, x30, [sp], #16
|
|
ret
|
|
|
|
/*
|
|
* Write a register in the DCFG block
|
|
* in: x0 = offset
|
|
* in: w1 = value to write
|
|
* uses x0, x1, x2
|
|
*/
|
|
_write_reg_dcfg:
|
|
ldr x2, =NXP_DCFG_ADDR
|
|
str w1, [x2, x0]
|
|
ret
|
|
|
|
/*
|
|
* Read a register in the DCFG block
|
|
* in: x0 = offset
|
|
* out: w0 = value read
|
|
* uses x0, x1, x2
|
|
*/
|
|
_read_reg_dcfg:
|
|
ldr x2, =NXP_DCFG_ADDR
|
|
ldr w1, [x2, x0]
|
|
mov w0, w1
|
|
ret
|
|
|
|
/*
|
|
* This function returns an mpidr value for a core, given a core_mask_lsb
|
|
* in: x0 = core mask lsb
|
|
* out: x0 = affinity2:affinity1:affinity0, where affinity is 8-bits
|
|
* uses x0, x1
|
|
*/
|
|
get_mpidr_value:
|
|
/* Convert a core mask to an SoC core number */
|
|
clz w0, w0
|
|
mov w1, #31
|
|
sub w0, w1, w0
|
|
|
|
/* Get the mpidr core number from the SoC core number */
|
|
mov w1, wzr
|
|
tst x0, #1
|
|
b.eq 1f
|
|
orr w1, w1, #1
|
|
1:
|
|
/* Extract the cluster number */
|
|
lsr w0, w0, #1
|
|
orr w0, w1, w0, lsl #8
|
|
|
|
ret
|
|
|
|
/*
|
|
* This function returns the redistributor base address for the core specified
|
|
* in x1
|
|
* in: x0 - core mask lsb of specified core
|
|
* out: x0 = redistributor rd base address for specified core
|
|
* uses x0, x1, x2
|
|
*/
|
|
get_gic_rd_base:
|
|
/* Get the 0-based core number */
|
|
clz w1, w0
|
|
mov w2, #0x20
|
|
sub w2, w2, w1
|
|
sub w2, w2, #1
|
|
|
|
/* x2 = core number / loop counter */
|
|
ldr x0, =NXP_GICR_ADDR
|
|
mov x1, #GIC_RD_OFFSET
|
|
2:
|
|
cbz x2, 1f
|
|
add x0, x0, x1
|
|
sub x2, x2, #1
|
|
b 2b
|
|
1:
|
|
ret
|
|
|
|
/*
|
|
* This function returns the redistributor base address for the core specified
|
|
* in x1
|
|
* in: x0 - core mask lsb of specified core
|
|
* out: x0 = redistributor sgi base address for specified core
|
|
* uses x0, x1, x2
|
|
*/
|
|
get_gic_sgi_base:
|
|
/* Get the 0-based core number */
|
|
clz w1, w0
|
|
mov w2, #0x20
|
|
sub w2, w2, w1
|
|
sub w2, w2, #1
|
|
|
|
/* x2 = core number / loop counter */
|
|
ldr x0, =NXP_GICR_SGI_ADDR
|
|
mov x1, #GIC_SGI_OFFSET
|
|
2:
|
|
cbz x2, 1f
|
|
add x0, x0, x1
|
|
sub x2, x2, #1
|
|
b 2b
|
|
1:
|
|
ret
|
|
|
|
/*
|
|
* Write a register in the RESET block
|
|
* in: x0 = offset
|
|
* in: w1 = value to write
|
|
* uses x0, x1, x2
|
|
*/
|
|
_write_reg_reset:
|
|
ldr x2, =NXP_RESET_ADDR
|
|
str w1, [x2, x0]
|
|
ret
|
|
|
|
/*
|
|
* Read a register in the RESET block
|
|
* in: x0 = offset
|
|
* out: w0 = value read
|
|
* uses x0, x1
|
|
*/
|
|
_read_reg_reset:
|
|
ldr x1, =NXP_RESET_ADDR
|
|
ldr w0, [x1, x0]
|
|
ret
|