230 lines
6.1 KiB
C
230 lines
6.1 KiB
C
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include "dcfg_lsch3.h"
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#include "soc_default_base_addr.h"
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#include "soc_default_helper_macros.h"
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/*
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* SVR Definition of LS1088A
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* A: without security
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* AE: with security
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* (not include major and minor rev)
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*/
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#define SVR_LS1044A 0x870323
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#define SVR_LS1044AE 0x870322
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#define SVR_LS1048A 0x870321
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#define SVR_LS1048AE 0x870320
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#define SVR_LS1084A 0x870303
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#define SVR_LS1084AE 0x870302
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#define SVR_LS1088A 0x870301
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#define SVR_LS1088AE 0x870300
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#define SVR_WO_E 0xFFFFFE
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/* Number of cores in platform */
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#define NUMBER_OF_CLUSTERS 2
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#define CORES_PER_CLUSTER 4
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#define PLATFORM_CORE_COUNT (NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER)
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/* set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS 1
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#define NUM_DRAM_REGIONS 2
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#define NXP_DRAM0_ADDR 0x80000000
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#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
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#define NXP_DRAM1_ADDR 0x8080000000
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#define NXP_DRAM1_MAX_SIZE 0x7F80000000 /* 510 G */
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/* DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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#define NXP_POWMGTDCR 0x700123C20
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/* epu register offsets and values */
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#define EPU_EPGCR_OFFSET 0x0
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#define EPU_EPIMCR10_OFFSET 0x128
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#define EPU_EPCTR10_OFFSET 0xa28
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#define EPU_EPCCR10_OFFSET 0x828
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#ifdef EPU_EPCCR10_VAL
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#undef EPU_EPCCR10_VAL
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#endif
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#define EPU_EPCCR10_VAL 0xf2800000
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#define EPU_EPIMCR10_VAL 0xba000000
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#define EPU_EPCTR10_VAL 0x0
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#define EPU_EPGCR_VAL (1 << 31)
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/* pmu register offsets and values */
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#define PMU_PCPW20SR_OFFSET 0x830
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#define PMU_CLAINACTSETR_OFFSET 0x1100
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#define PMU_CLAINACTCLRR_OFFSET 0x1104
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#define PMU_CLSINACTSETR_OFFSET 0x1108
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#define PMU_CLSINACTCLRR_OFFSET 0x110C
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#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
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#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114
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#define PMU_CLL2FLUSHSR_OFFSET 0x1118
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#define PMU_POWMGTCSR_OFFSET 0x4000
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#define PMU_IPPDEXPCR0_OFFSET 0x4040
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#define PMU_IPPDEXPCR1_OFFSET 0x4044
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#define PMU_IPPDEXPCR2_OFFSET 0x4048
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#define PMU_IPPDEXPCR3_OFFSET 0x404C
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#define PMU_IPPDEXPCR4_OFFSET 0x4050
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#define PMU_IPPDEXPCR5_OFFSET 0x4054
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#define PMU_IPSTPCR0_OFFSET 0x4120
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#define PMU_IPSTPCR1_OFFSET 0x4124
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#define PMU_IPSTPCR2_OFFSET 0x4128
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#define PMU_IPSTPCR3_OFFSET 0x412C
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#define PMU_IPSTPCR4_OFFSET 0x4130
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#define PMU_IPSTPCR5_OFFSET 0x4134
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#define PMU_IPSTPCR6_OFFSET 0x4138
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#define PMU_IPSTPACK0_OFFSET 0x4140
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#define PMU_IPSTPACK1_OFFSET 0x4144
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#define PMU_IPSTPACK2_OFFSET 0x4148
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#define PMU_IPSTPACK3_OFFSET 0x414C
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#define PMU_IPSTPACK4_OFFSET 0x4150
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#define PMU_IPSTPACK5_OFFSET 0x4154
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#define PMU_IPSTPACK6_OFFSET 0x4158
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#define PMU_POWMGTCSR_VAL (1 << 20)
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#define IPPDEXPCR0_MASK 0xFFFFFFFF
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#define IPPDEXPCR1_MASK 0xFFFFFFFF
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#define IPPDEXPCR2_MASK 0xFFFFFFFF
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#define IPPDEXPCR3_MASK 0xFFFFFFFF
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#define IPPDEXPCR4_MASK 0xFFFFFFFF
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#define IPPDEXPCR5_MASK 0xFFFFFFFF
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/* DEVDISR5_FLX_TMR */
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#define IPPDEXPCR_FLX_TMR 0x00004000
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#define DEVDISR5_FLX_TMR 0x00004000
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#define IPSTPCR0_VALUE 0x0041310C
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#define IPSTPCR1_VALUE 0x000003FF
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#define IPSTPCR2_VALUE 0x00013006
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/* Dont' stop UART */
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#define IPSTPCR3_VALUE 0x0000033A
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#define IPSTPCR4_VALUE 0x00103300
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#define IPSTPCR5_VALUE 0x00000001
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#define IPSTPCR6_VALUE 0x00000000
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#define TZPC_BLOCK_SIZE 0x1000
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/* PORSR1 */
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#define PORSR1_RCW_MASK 0xFF800000
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#define PORSR1_RCW_SHIFT 23
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/* CFG_RCW_SRC[6:0] */
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#define RCW_SRC_TYPE_MASK 0x70
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/* RCW SRC NOR */
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#define NOR_16B_VAL 0x20
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/*
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* RCW SRC Serial Flash
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* 1. SERAIL NOR (QSPI)
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* 2. OTHERS (SD/MMC, SPI, I2C1)
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*/
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#define RCW_SRC_SERIAL_MASK 0x7F
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#define QSPI_VAL 0x62
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#define SDHC_VAL 0x40
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#define EMMC_VAL 0x41
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/*
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* Required LS standard platform porting definitions
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* for CCN-504 - Read from RN-F node ID register
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*/
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#define PLAT_CLUSTER_TO_CCN_ID_MAP 1, 9, 11, 19
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
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/*
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* Clock Divisors
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*/
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#define NXP_PLATFORM_CLK_DIVIDER 1
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#define NXP_UART_CLK_DIVIDER 2
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/* dcfg register offsets and values */
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#define DCFG_DEVDISR1_OFFSET 0x70
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#define DCFG_DEVDISR2_OFFSET 0x74
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#define DCFG_DEVDISR3_OFFSET 0x78
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#define DCFG_DEVDISR5_OFFSET 0x80
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#define DCFG_DEVDISR6_OFFSET 0x84
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#define DCFG_DEVDISR1_SEC (1 << 22)
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#define DCFG_DEVDISR3_QBMAIN (1 << 12)
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#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
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#define DCFG_DEVDISR5_MEM (1 << 0)
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#define DEVDISR1_VALUE 0x0041310c
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#define DEVDISR2_VALUE 0x000003ff
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#define DEVDISR3_VALUE 0x00013006
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#define DEVDISR4_VALUE 0x0000033e
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#define DEVDISR5_VALUE 0x00103300
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#define DEVDISR6_VALUE 0x00000001
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/*
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* pwr mgmt features supported in the soc-specific code:
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* value == 0x0, the soc code does not support this feature
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* value != 0x0, the soc code supports this feature
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*/
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#define SOC_CORE_RELEASE 0x1
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#define SOC_CORE_RESTART 0x1
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#define SOC_CORE_OFF 0x1
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#define SOC_CORE_STANDBY 0x1
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#define SOC_CORE_PWR_DWN 0x1
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#define SOC_CLUSTER_STANDBY 0x1
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#define SOC_CLUSTER_PWR_DWN 0x1
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#define SOC_SYSTEM_STANDBY 0x1
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#define SOC_SYSTEM_PWR_DWN 0x1
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#define SOC_SYSTEM_OFF 0x1
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#define SOC_SYSTEM_RESET 0x1
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#define SYSTEM_PWR_DOMAINS 1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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NUMBER_OF_CLUSTERS + \
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SYSTEM_PWR_DOMAINS)
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/* Power state coordination occurs at the system level */
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#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
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/* Local power state for power domains in Run state */
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#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
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/* define retention state */
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
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#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
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/* define power-down state */
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
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#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
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#ifndef __ASSEMBLER__
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/* CCI slave interfaces */
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static const int cci_map[] = {
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3,
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4,
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};
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void soc_init_lowlevel(void);
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void soc_init_percpu(void);
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void _soc_set_start_addr(unsigned long addr);
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void _set_platform_security(void);
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#endif
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#endif /* SOC_H */
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