236 lines
8.3 KiB
C
236 lines
8.3 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <smcc_helpers.h>
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#include <string.h>
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/*******************************************************************************
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* Context management library initialisation routine. This library is used by
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* runtime services to share pointers to 'cpu_context' structures for the secure
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* and non-secure states. Management of the structures and their associated
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* memory is not done by the context management library e.g. the PSCI service
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* manages the cpu context used for entry from and exit to the non-secure state.
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* The Secure payload manages the context(s) corresponding to the secure state.
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* It also uses this library to get access to the non-secure
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* state cpu context pointers.
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******************************************************************************/
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void cm_init(void)
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{
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/*
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* The context management library has only global data to initialize, but
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* that will be done when the BSS is zeroed out
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*/
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}
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/*******************************************************************************
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* The following function initializes the cpu_context 'ctx' for
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* first use, and sets the initial entrypoint state as specified by the
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* entry_point_info structure.
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*
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* The security state to initialize is determined by the SECURE attribute
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* of the entry_point_info. The function returns a pointer to the initialized
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* context and sets this as the next context to return to.
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*
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* The EE and ST attributes are used to configure the endianness and secure
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* timer availability for the new execution context.
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*
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* To prepare the register state for entry call cm_prepare_el3_exit() and
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* el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
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* cm_e1_sysreg_context_restore().
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******************************************************************************/
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static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
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{
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unsigned int security_state;
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uint32_t scr, sctlr;
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regs_t *reg_ctx;
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assert(ctx);
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security_state = GET_SECURITY_STATE(ep->h.attr);
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/* Clear any residual register values from the context */
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memset(ctx, 0, sizeof(*ctx));
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reg_ctx = get_regs_ctx(ctx);
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/*
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* Base the context SCR on the current value, adjust for entry point
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* specific requirements
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*/
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scr = read_scr();
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scr &= ~(SCR_NS_BIT | SCR_HCE_BIT);
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if (security_state != SECURE)
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scr |= SCR_NS_BIT;
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/*
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* Set up SCTLR for the Non Secure context.
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* EE bit is taken from the entrypoint attributes
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* M, C and I bits must be zero (as required by PSCI specification)
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*
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* The target exception level is based on the spsr mode requested.
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* If execution is requested to hyp mode, HVC is enabled
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* via SCR.HCE.
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*
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* Always compute the SCTLR_EL1 value and save in the cpu_context
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* - the HYP registers are set up by cm_preapre_ns_entry() as they
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* are not part of the stored cpu_context
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*
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* TODO: In debug builds the spsr should be validated and checked
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* against the CPU support, security state, endianness and pc
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*/
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if (security_state != SECURE) {
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sctlr = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0;
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sctlr |= SCTLR_RES1;
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write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr);
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}
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if (GET_M32(ep->spsr) == MODE32_hyp)
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scr |= SCR_HCE_BIT;
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write_ctx_reg(reg_ctx, CTX_SCR, scr);
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write_ctx_reg(reg_ctx, CTX_LR, ep->pc);
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write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr);
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/*
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* Store the r0-r3 value from the entrypoint into the context
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* Use memcpy as we are in control of the layout of the structures
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*/
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memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t));
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}
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/*******************************************************************************
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* The following function initializes the cpu_context for a CPU specified by
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* its `cpu_idx` for first use, and sets the initial entrypoint state as
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* specified by the entry_point_info structure.
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******************************************************************************/
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void cm_init_context_by_index(unsigned int cpu_idx,
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const entry_point_info_t *ep)
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{
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cpu_context_t *ctx;
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ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
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cm_init_context_common(ctx, ep);
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}
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/*******************************************************************************
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* The following function initializes the cpu_context for the current CPU
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* for first use, and sets the initial entrypoint state as specified by the
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* entry_point_info structure.
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******************************************************************************/
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void cm_init_my_context(const entry_point_info_t *ep)
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{
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cpu_context_t *ctx;
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ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
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cm_init_context_common(ctx, ep);
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}
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/*******************************************************************************
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* Prepare the CPU system registers for first entry into secure or normal world
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*
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* If execution is requested to hyp mode, HSCTLR is initialized
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* If execution is requested to non-secure PL1, and the CPU supports
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* HYP mode then HYP mode is disabled by configuring all necessary HYP mode
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* registers.
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******************************************************************************/
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void cm_prepare_el3_exit(uint32_t security_state)
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{
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uint32_t sctlr, scr, hcptr;
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cpu_context_t *ctx = cm_get_context(security_state);
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assert(ctx);
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if (security_state == NON_SECURE) {
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scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR);
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if (scr & SCR_HCE_BIT) {
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/* Use SCTLR value to initialize HSCTLR */
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sctlr = read_ctx_reg(get_regs_ctx(ctx),
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CTX_NS_SCTLR);
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sctlr |= HSCTLR_RES1;
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/* Temporarily set the NS bit to access HSCTLR */
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write_scr(read_scr() | SCR_NS_BIT);
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/*
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* Make sure the write to SCR is complete so that
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* we can access HSCTLR
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*/
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isb();
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write_hsctlr(sctlr);
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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isb();
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} else if (read_id_pfr1() &
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(ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) {
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/* Set the NS bit to access HCR, HCPTR, CNTHCTL, VPIDR, VMPIDR */
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write_scr(read_scr() | SCR_NS_BIT);
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isb();
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/* PL2 present but unused, need to disable safely */
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write_hcr(0);
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/* HSCTLR : can be ignored when bypassing */
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/* HCPTR : disable all traps TCPAC, TTA, TCP */
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hcptr = read_hcptr();
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hcptr &= ~(TCPAC_BIT | TTA_BIT | TCP11_BIT | TCP10_BIT);
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write_hcptr(hcptr);
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/* Enable EL1 access to timer */
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write_cnthctl(PL1PCEN_BIT | PL1PCTEN_BIT);
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/* Reset CNTVOFF_EL2 */
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write64_cntvoff(0);
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/* Set VPIDR, VMPIDR to match MIDR, MPIDR */
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write_vpidr(read_midr());
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write_vmpidr(read_mpidr());
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/*
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* Reset VTTBR.
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* Needed because cache maintenance operations depend on
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* the VMID even when non-secure EL1&0 stage 2 address
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* translation are disabled.
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*/
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write64_vttbr(0);
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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isb();
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}
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}
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}
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