129 lines
4.6 KiB
ArmAsm
129 lines
4.6 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#include "../drivers/pwrc/fvp_pwrc.h"
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#include "../fvp_def.h"
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.globl plat_secondary_cold_boot_setup
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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/* --------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* For AArch32, cold-booting secondary CPUs is not yet
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* implemented and they panic.
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* --------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and warm
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* boot. On FVP, this information can be queried from the power
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* controller. The Power Control SYS Status Register (PSYSR) indicates
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* the wake-up reason for the CPU.
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*
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* For a cold boot, return 0.
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* For a warm boot, read the mailbox and return the address it contains.
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*
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* TODO: PSYSR is a common register and should be
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* accessed using locks. Since it is not possible
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* to use locks immediately after a cold reset
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* we are relying on the fact that after a cold
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* reset all cpus will read the same WK field
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* ---------------------------------------------------------------------
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* When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
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* WakeRequest signal" then it is a warm boot.
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* ---------------------------------------------------------------------
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*/
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ldcopr r2, MPIDR
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ldr r1, =PWRC_BASE
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str r2, [r1, #PSYSR_OFF]
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ldr r2, [r1, #PSYSR_OFF]
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ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
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cmp r2, #WKUP_PPONR
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beq warm_reset
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cmp r2, #WKUP_GICREQ
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beq warm_reset
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/* Cold reset */
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mov r0, #0
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bx lr
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warm_reset:
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/* ---------------------------------------------------------------------
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* A mailbox is maintained in the trusted SRAM. It is flushed out of the
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* caches after every update using normal memory so it is safe to read
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* it here with SO attributes.
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* ---------------------------------------------------------------------
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*/
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ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr r0, [r0]
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cmp r0, #0
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beq _panic
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bx lr
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/* ---------------------------------------------------------------------
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* The power controller indicates this is a warm reset but the mailbox
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* is empty. This should never happen!
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* ---------------------------------------------------------------------
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*/
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_panic:
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b _panic
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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ldcopr r0, MPIDR
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ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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and r0, r1
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cmp r0, #FVP_PRIMARY_CPU
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moveq r0, #1
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movne r0, #0
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bx lr
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endfunc plat_is_my_cpu_primary
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